 Vincent Liu
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090263eff6
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[VLM] avoid CUDA placement on non-CUDA platforms (#38750)
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2026-09-19 11:13:22 +08:00 |
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Xiaoyu Zhang
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986959e3c4
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[Refactor] Deduplicate kernel helpers and remove unused code (#40197)
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2026-09-19 09:27:30 +08:00 |
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Khoa PhamandCursor
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10b0bcfd18
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[PD] Allow decode radix cache and HiCache L1/L2 with DCP (#40263)
Co-authored-by: Cursor <cursoragent@cursor.com>
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2026-09-18 17:54:35 -07:00 |
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Liangsheng Yin
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d507accadc
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[Test] Drop dead and strictly-subsumed CI test registrations (#40264)
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2026-09-18 17:49:13 -07:00 |
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Cheng Wan
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fa7e83fd09
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Name the two widths of the WORLD group (#40070)
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2026-09-18 17:47:02 -07:00 |
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Cheng Wan
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81421b91e9
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One read path for every parallel name (#40069)
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2026-09-18 17:43:56 -07:00 |
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Cheng Wan
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afe71f4b9e
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Read process groups through the runtime context (#40068)
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2026-09-18 17:40:32 -07:00 |
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5931fd60ee
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Support unified memory page-envelope transfers in PD (#39477)
Co-authored-by: yhzhuang <yhzhuang@fb.com>
Co-authored-by: Lianmin Zheng <lianminzheng@gmail.com>
Co-authored-by: Yonghao Zhuang <yhzhuang@users.noreply.github.com>
Co-authored-by: Cheng Wan <cheng.wan@radixark.ai>
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2026-09-18 17:39:50 -07:00 |
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Cheng Wan
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d0730a0e8b
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Give the attention-DP width and rank one home (#40067)
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2026-09-18 17:34:33 -07:00 |
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Lifan Shen
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8ea0ee300d
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perf(sampling): avoid GPU syncs when applying custom logit processors (#39234)
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2026-09-18 17:09:30 -07:00 |
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Alison ShaoandXinyuan Tong
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21e6c98ccb
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Fix corrupted chat prompts on mistral_common tokenizers (tool_choice auto never fires) (#39773)
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
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2026-09-18 16:12:06 -07:00 |
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2394b231c2
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Fix Mistral3 retaining every vision-tower layer to read one (#39185)
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
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2026-09-18 16:11:54 -07:00 |
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Zhiqiang Xieandcctry
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ceb1d2e580
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[PD] Enable optimistic prefill with buffer-only L3 write-through HiCache (#40043)
Co-authored-by: cctry <csycfl@gmail.com>
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2026-09-18 16:04:15 -07:00 |
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5e4b94b134
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[MM] Skip VMM error gathers for text-only requests (#40005)
Co-authored-by: metamergebot <324680979+metamergebot@users.noreply.github.com>
Co-authored-by: Jialin Ouyang <Jialin.Ouyang@gmail.com>
Co-authored-by: Lianmin Zheng <lianminzheng@gmail.com>
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2026-09-18 16:00:43 -07:00 |
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Jialin Ouyang
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f3851486cb
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[Perf] Fuse SWA page lookup and mapping clear (#38948)
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2026-09-18 15:51:07 -07:00 |
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81a199f56a
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[HiCache] Read the in-flight buffer backup's node id from its snapshot in sanity_check (#40013)
Co-authored-by: Pranjal Shankhdhar <pranjalssh@meta.com>
Co-authored-by: Jialin Ouyang <Jialin.Ouyang@gmail.com>
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2026-09-18 15:47:56 -07:00 |
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0e5347db82
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Support MXFP8 and deferred route weighting in DeepEP v2 (#40030)
Co-authored-by: metamergebot <324680979+metamergebot@users.noreply.github.com>
Co-authored-by: Xingyu Liu <38244988+charlotte12l@users.noreply.github.com>
Co-authored-by: pranjalssh <14260275+pranjalssh@users.noreply.github.com>
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2026-09-18 15:40:38 -07:00 |
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Liangsheng Yin
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6cc9090d1f
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[mem_cache] Release up to owned_kv_len on radix cache insert (#40075)
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2026-09-18 15:37:52 -07:00 |
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Zhiqiang Xie
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a0534f8cca
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[HiCache] Stop arming a prefetch retry for a too-short storage span (#40042)
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2026-09-18 15:33:58 -07:00 |
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Sam (Kesen Li)
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d346b214fb
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feat(kv-cache): support SM100 NVFP4 GenMHA and speculative decoding (#36340)
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2026-09-18 14:50:46 -07:00 |
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metamergebotandcctry
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6a9c7001d3
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[Logprob] Borrow graph-pool memory for input logprob logits construction (#40007)
Co-authored-by: cctry <csycfl@gmail.com>
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2026-09-18 13:18:01 -07:00 |
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Jialin Ouyang
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da2f434951
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[Spec] Add explicit prefill shared-read capability for plugins (#39502)
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2026-09-18 13:11:01 -07:00 |
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Lianmin Zhengandraghotham
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248c202b46
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Use runtime token widths for Triton speculative verification (#39859)
Co-authored-by: raghotham <853234+raghotham@users.noreply.github.com>
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2026-09-18 11:07:55 -07:00 |
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Lianmin Zheng
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6bd1a0af1d
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Add registration for external model configurations (#39452)
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2026-09-18 10:06:24 -07:00 |
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81363bf8cb
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[kernel] Share the warp vectorized copy and enforce its alignment (#36176)
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Co-authored-by: BBuf <1182563586@qq.com>
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2026-09-18 22:40:54 +08:00 |
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a6cf05817f
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dsv4.1: remaining model and runtime integration (#38798)
Co-authored-by: BBuf <1182563586@qq.com>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Co-authored-by: Xiaoyu Zhang <xiaoyu.zhang@radixark.ai>
Co-authored-by: Yuwei An <ayw.sirius19@gmail.com>
Co-authored-by: Khoa Pham <khoa.pham@radixark.ai>
Co-authored-by: Yuhao Yang <47235274+yhyang201@users.noreply.github.com>
Co-authored-by: Zhichen Zeng <zczeng@uw.edu>
Co-authored-by: Ke Bao <ispobaoke@gmail.com>
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2026-09-18 02:55:30 -07:00 |
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Liangsheng Yin
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1b200ffaaa
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[Quant] Serve 32-wide-K ue8m0 block-FP8 linears through the FlashInfer MXFP8 GEMMs (#40039)
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2026-09-18 02:51:12 -07:00 |
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Shu Wang
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1e8699fda3
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[NVIDIA][comm] Merge EP+MoE-TP post-experts all-reduces into one _TP reduction (#32963)
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2026-09-18 01:35:10 -07:00 |
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zhaozx-cn
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8ac39c66d8
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[NPU] support kimi k3 on A5 and improve performance (#39589)
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2026-09-18 16:33:54 +08:00 |
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Rumit DesaiandXiaoyu Zhang
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1fdd6c8921
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[Runtime] Let out-of-tree platforms provide full graph backends (#37969)
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
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2026-09-18 15:42:46 +08:00 |
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iridiumine
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f86f60081d
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[NPU] Adapt hicache for K3 hybrid models (#39415)
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2026-09-18 14:48:20 +08:00 |
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Jensen
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3ce3b4969f
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[NPU] Avoid repeated BF16 wo_a weight transposes in DeepSeek-V4 decode (#39919)
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2026-09-18 09:10:43 +03:00 |
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maithilijoshi20
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0dad91d50f
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Fix int4 MoE tuner config filename (#35260)
Signed-off-by: maithilijoshi20 <maithilij2003@gmail.com>
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2026-09-18 13:56:38 +08:00 |
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Yuwei An
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65ef55e2a8
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[Scheduler] Add shortest-prefill-first scheduling (#40024)
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2026-09-17 21:18:58 -07:00 |
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Mohammad Miadh AngkadandMohammad Angkad
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c055dc6ff6
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[CI] Check B200 NUMA mapping against sysfs numa_node (#40055)
Co-authored-by: Mohammad Angkad <mohammad.angkad@radixark.ai>
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2026-09-17 21:14:47 -07:00 |
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db39b7f961
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[Fix] Guard conditional top-logprob keys in the completions echo path (#34776)
Co-authored-by: James Liu <jamesl@modal.com>
Co-authored-by: hnyls2002 <lsyincs@gmail.com>
Co-authored-by: Liangsheng Yin <hnyls2002@gmail.com>
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2026-09-17 19:47:26 -07:00 |
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Nan Jiang
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740f57a02c
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[Spec] Fix CDF boundary handling in TreeSpeculativeSamplingTargetOnly (#35798)
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2026-09-17 19:41:52 -07:00 |
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William Arnoldandishandhanani
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0214954f26
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[gRPC] Stream engine state changes (#39915)
Signed-off-by: William Arnold <7565007+Aphoh@users.noreply.github.com>
Co-authored-by: ishandhanani <82981111+ishandhanani@users.noreply.github.com>
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2026-09-17 19:17:25 -07:00 |
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Liangsheng Yin
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f65c70bb7d
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[Kernel] Move CUDA and ROCm speculative kernels to JIT (#40033)
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2026-09-17 17:27:26 -07:00 |
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Nan Jiang
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20518d8518
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[Scheduler] Align RadixCache no-insert cleanup with kv_len_to_handle (#35204)
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2026-09-17 17:00:59 -07:00 |
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Xiaoyu Zhang
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7bc9152447
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[Test] Consolidate kernel tests under plural kernels tree (#39966)
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2026-09-18 07:37:48 +08:00 |
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Liangsheng Yin
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1f0c73e9bd
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[DSV4] Generalize attention metadata, sparse prefill, and KV pool over compress ratios (#39921)
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2026-09-17 15:55:19 -07:00 |
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Thomas Wang
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6c73368c32
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[AMD][DSV4] Enable hicache on deepseek-v4 fp8 unified attn (#37778)
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2026-09-17 11:29:23 -07:00 |
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1f60ddef5d
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[PD] Introduce runtime role switching between prefill and decode (#28403)
Signed-off-by: huanglong <huanglong@linux.alibaba.com>
Signed-off-by: inkcherry <mingzhi.liu@amd.com>
Co-authored-by: huanglong <huanglong@linux.alibaba.com>
Co-authored-by: Shangming Cai <csmthu@gmail.com>
Co-authored-by: Huang Long <121648372+LLLL114@users.noreply.github.com>
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2026-09-18 01:45:12 +08:00 |
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Byron HsuandByron Hsu
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a98d921658
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[DP Attn] Fix crash for no token all-gather case (#39899)
Co-authored-by: Byron Hsu <byron+per@periodiclabs.ai>
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2026-09-17 09:21:09 -07:00 |
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25c9f724d4
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fix(multimodal): handle tensor images in exact-token preprocessing (#30368)
Signed-off-by: Zhuangcheng(Jesse) Gu <zcgu@connect.hku.hk>
Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
Co-authored-by: Mick <mickjagger19@icloud.com>
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2026-09-17 09:20:21 -07:00 |
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vstone-w
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a9fb1c3238
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dsv4(npu): support prefill context parallelism with interleave and zigzag (#39427)
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2026-09-17 19:59:41 +08:00 |
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Shuwen Wang
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6ca866ea29
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[HiCache][Perf] fix: batch HiCache D2H submits per step for hybrid pools (#39050)
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2026-09-17 17:53:58 +08:00 |
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yl3469andShuwen Wang
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1a90ae6727
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Add Agentic-Aware Tail-Optimized LRU eviction to the unified radix cache (#34012)
Co-authored-by: Shuwen Wang <47200617+alphabetc1@users.noreply.github.com>
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2026-09-17 17:52:59 +08:00 |
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e970453b43
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[NPU]Refactor weight processing and add NPUSwigluLimit activation (#38420)
Co-authored-by: AndyLi429 <AndyLi429@noreply.gitcode.com>
Co-authored-by: Even Zhou <even.y.zhou@outlook.com>
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2026-09-17 16:40:32 +08:00 |
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