 Xinyuan Tong
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bed20249f1
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fix(tool_call): reland schema type normalization (#26433)
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2026-05-28 14:31:18 +08:00 |
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Khoa PhamandClaude Opus 4.7
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9040feebd8
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[Gemma4] Add test for MTP models (#24552)
Co-authored-by: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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2026-05-27 21:36:28 -07:00 |
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MingxuZh
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21ba329dac
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[Xeon] CPU CI enhancement for Intel Xeon platforms (#24649)
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2026-05-28 10:49:04 +08:00 |
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Bingxu ChenandCursor
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81663cb5f1
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[AMD] [CI] Register MI35x GSM8K nightly tests (#26478)
Co-authored-by: Cursor <cursoragent@cursor.com>
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2026-05-28 10:31:43 +08:00 |
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Baizhou ZhangandClaude Opus 4.7
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68e5b4fdd6
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[NemotronH] Fix weight-loading unit test broken by Puzzle support (#26522)
Co-authored-by: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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2026-05-27 17:44:45 -07:00 |
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+2
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deaba74745
|
[AMD][DSV4] DSV4 MTP graph + sparse triton attn optimizations (#26383)
Co-authored-by: wunhuang <wunhuang@amd.com>
Co-authored-by: Thomas Wang <1am9trash@gmail.com>
Co-authored-by: Xinyi Song <86638975+RolaoDenthu@users.noreply.github.com>
Co-authored-by: HaiShaw <hixiao@gmail.com>
Co-authored-by: amd-danli103 <danli103@amd.com>
Co-authored-by: Lin, Soga <soga.lin@amd.com>
Co-authored-by: Raiden-Makoto <Raiden-Makoto@users.noreply.github.com>
Co-authored-by: Hubert Lu <55214931+hubertlu-tw@users.noreply.github.com>
Co-authored-by: yichiche@amd.com <jacky.cheng>
Co-authored-by: yctseng0211 <yctseng@amd.com>
Co-authored-by: Bingxu Chen <bingxche@amd.com>
|
2026-05-27 15:23:35 -07:00 |
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19663aafcd
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Support batch size > 1 when enable CP (#23269)
Co-authored-by: Shunkang <182541032+Shunkangz@users.noreply.github.co>
Co-authored-by: Khoa Pham <khoa.pham@radixark.ai>
Co-authored-by: Baizhou Zhang <sobereddiezhang@gmail.com>
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2026-05-27 14:11:17 -07:00 |
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Kaixi Hou
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ddf0627254
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[NVIDIA] [GDN] Add FlashInfer prefill support for SM100+ (Blackwell) (#22921)
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2026-05-27 13:58:05 -07:00 |
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Sam HandYihao Wang
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a95b4e2e09
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[Feature] WebSocket streaming audio input for ASR (#22848)
Co-authored-by: Yihao Wang <42559837+AgainstEntropy@users.noreply.github.com>
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2026-05-27 22:44:55 +08:00 |
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weireweireandZhangheng
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034dd39189
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Support KV events for UnifiedRadixCache (#26387)
Co-authored-by: Zhangheng <hzh0425@apache.org>
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2026-05-27 22:10:40 +08:00 |
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Jialin Ouyang
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98bc6f3c22
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API Perf: Replace pydantic per-element validation with C loop validation (#26355)
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2026-05-27 02:04:07 -07:00 |
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Jacob0226
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d44584e8d8
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[AMD] [CI] Add GLM-5.1 MXFP4 TP2 accuracy gate (#26396)
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2026-05-27 01:49:48 -07:00 |
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Jacob0226andCursor
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bf5bc23431
|
[AMD] [CI] Add DeepSeek-R1-0528 FP8 HiCache GSM8K test on MI35x (#26395)
Co-authored-by: Cursor <cursoragent@cursor.com>
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2026-05-27 01:48:38 -07:00 |
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d45ee3f6c5
|
[HiCache] fix: Mooncake Dummy Client mode for hybrid Mamba models (#25278)
Co-authored-by: Cursor Agent <cursoragent@cursor.com>
Co-authored-by: Teng Ma <stmatengss@users.noreply.github.com>
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2026-05-27 10:29:52 +08:00 |
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vikram singh shekhawatandMa Mingfei
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737c6cd6d1
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[XPU] Add registry mechanism for XPU CI tests (#25405)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
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2026-05-27 08:56:59 +08:00 |
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Joel Schlosser
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6989fede3c
|
Purge usage of pytorch named tensors (#25911)
|
2026-05-26 14:58:57 -07:00 |
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Ziang Li
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2b1e53c98d
|
[RL] Fix FP8 skip matching for trailing-dot prefixes (#26287)
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2026-05-26 20:30:08 +00:00 |
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Liangsheng Yin
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ec6f8d61f7
|
[Spec] Async-assert probes across EAGLE/MTP; zero tgt_cache_loc (#26335)
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2026-05-26 11:34:03 -07:00 |
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Zhangheng
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38f32c38ab
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[UnifiedRadixTree]: Support L3 HiStorage framework (#26062)
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2026-05-26 22:38:00 +08:00 |
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Jun Liu
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c47f0e7cdd
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[PD] Fix top logprobs crash in prefill path (#26299)
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2026-05-26 22:01:10 +08:00 |
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roikoren755
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e958f4561f
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[feat] Support extra_buffer in Mamba2-based models (#15829)
Signed-off-by: Roi Koren <roik@nvidia.com>
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2026-05-26 16:03:29 +08:00 |
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Liangsheng Yin
|
7e6e5efe51
|
Revert "fix(tool_call): normalize non-standard JSON Schema types in tool params" (#26379)
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2026-05-26 00:49:41 -07:00 |
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Yuan Luoandluoyuan.luo
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d34d4d9f5f
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[GDN] Support SM100 CuTeDSL GDN Prefill Kernel (#26200)
Co-authored-by: luoyuan.luo <luoyuan.luo@antgroup.com>
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2026-05-26 15:38:29 +08:00 |
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Xinyuan Tong
|
64c7c6851b
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fix(tool_call): normalize non-standard JSON Schema types in tool params (#23476)
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2026-05-26 15:23:59 +08:00 |
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+2
|
3f5e2c7688
|
[AMD] Dsv4/pr2 compressor opt (#26208)
Co-authored-by: wunhuang <wunhuang@amd.com>
Co-authored-by: Thomas Wang <1am9trash@gmail.com>
Co-authored-by: Xinyi Song <86638975+RolaoDenthu@users.noreply.github.com>
Co-authored-by: HaiShaw <hixiao@gmail.com>
Co-authored-by: amd-danli103 <danli103@amd.com>
Co-authored-by: Lin, Soga <soga.lin@amd.com>
Co-authored-by: Raiden-Makoto <Raiden-Makoto@users.noreply.github.com>
Co-authored-by: Hubert Lu <55214931+hubertlu-tw@users.noreply.github.com>
Co-authored-by: yichiche@amd.com <jacky.cheng>
Co-authored-by: yctseng0211 <yctseng@amd.com>
Co-authored-by: Bingxu Chen <bingxche@amd.com>
|
2026-05-25 23:54:40 -07:00 |
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mispa-msandMick
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3142278c5f
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[diffusion] feat: layerwise NVTX markers for Nsight Systems profiling (#25683)
Co-authored-by: Mick <mickjagger19@icloud.com>
|
2026-05-26 11:24:27 +08:00 |
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Ziang Li
|
2b9dd9c8b3
|
[FlashInfer v0.6.10] [RL] [DSv32] [GLM-5] Add --dsa-topk-backend and integrate FlashInfer and pytorch topk (#22851)
|
2026-05-25 13:08:03 -07:00 |
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Ke Bao
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b13d3d18c6
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Refactor HiCache stack dispatch into strategies (#26295)
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2026-05-26 00:06:17 +08:00 |
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Shangming Cai
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2aa6995308
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[CI] Enable EPD CI for EPD architecture enhancements (#26281)
|
2026-05-25 23:52:58 +08:00 |
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Shangming Cai
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bc8d64bf36
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[CI] Align score threshold in dsv4 disaggregation test (#26268)
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2026-05-25 17:48:45 +08:00 |
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Erik Wijmans
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87e69d57c4
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[lora] Fix overlap loading for cancelled requests (#25413)
|
2026-05-25 15:18:36 +09:00 |
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Xia WeiwenandMa Mingfei
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2bd3ac0b5d
|
[XPU] fix correctness issue of GDN triton kernel for XPU (#26065)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
|
2026-05-25 13:18:11 +08:00 |
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Ethan ZHUandZhangheng
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e86fdf3a3c
|
[Bug Fix][HiCache] TreeNode.get_prefix_hash_values @lru_cache can return mutated list (#26177)
Co-authored-by: Zhangheng <hzh0425@apache.org>
|
2026-05-25 11:15:10 +08:00 |
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Ma Mingfei
|
821d5f4a5b
|
[CPU] add faster KV-cache writes (#25874)
|
2026-05-25 10:28:52 +08:00 |
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Liangsheng Yin
|
d7e3e54148
|
[Test] split test/registered/distributed/ into topic folders (#26240)
|
2026-05-24 17:02:07 -07:00 |
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Liangsheng Yin
|
030bd5d3ed
|
[Test] test_session_latency: assert streaming tail/head stability (#26230)
|
2026-05-24 14:06:41 -07:00 |
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shuwenn
|
36eb72bf12
|
[UnifiedTree] fix: backup SWA-split parent before child under write-through (#25065)
|
2026-05-25 00:21:57 +08:00 |
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Dongjun Na
|
9d50cd9742
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[observability] add ServerArgs.stat_loggers for pluggable metrics backend (#24610)
Signed-off-by: Dongjun Na <kmu5544616@gmail.com>
|
2026-05-24 22:41:28 +08:00 |
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Mick
|
b6f71d5850
|
[VLM] avoid extra cuda-ipc staging for preprocessed input (#26096)
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2026-05-24 19:48:06 +08:00 |
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Khoa PhamandClaude Opus 4.7
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b0ce16d0c5
|
[CP] 1/N: Support MLA Prefill Context Parallel (#23292)
Co-authored-by: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
|
2026-05-23 03:07:09 -07:00 |
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liuxianglong17
|
8c78424701
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Reduce excessively long logs caused by transformer version updates. (#26033)
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2026-05-23 17:12:08 +08:00 |
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Baizhou Zhangandyhyang201
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7b7f1067bd
|
Add non-MTP DSV4 test coverage (#26141)
Co-authored-by: yhyang201 <yhyang201@gmail.com>
|
2026-05-22 19:43:17 -07:00 |
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weireweire
|
629b6c6a85
|
correct allreduce fusion and dummy_run alignment in SCATTERED MLP mode (moe_dense_tp_size=1) (#19918)
|
2026-05-22 19:18:25 -07:00 |
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nvjullin
|
cadfa2d025
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Support piecewise CUDA graph with NSA (#23351)
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2026-05-22 14:39:50 -07:00 |
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Kangyan-ZhouandClaude Opus 4.7
|
085777210c
|
feat(kv-events): expose structured KV-event publisher block on /server_info (#25844)
Co-authored-by: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
|
2026-05-23 01:59:45 +08:00 |
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Jialin Ouyangandjialino
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06c23d55b5
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perf: migrate Req token-id storage to array.array('q') in Scheduler (#25098)
Co-authored-by: jialino <jialino@fb.com>
|
2026-05-22 10:51:07 -07:00 |
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zhangtao2-1andzhangtao
|
6baa859a86
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Add MiniCPM5 tool call parser for XML-style function calls (#25600)
Co-authored-by: zhangtao <zhangtao2@modelbest.cn>
|
2026-05-22 23:09:40 +08:00 |
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Cheng WanandClaude Sonnet 4.6
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d765dfd043
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refactor(attn): init hisparse_coordinator before attn_backend; replace lazy property with init-time capture (#26012)
Co-authored-by: Claude Sonnet 4.6 (1M context) <noreply@anthropic.com>
|
2026-05-21 16:03:42 -07:00 |
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Cheng WanandClaude Sonnet 4.6
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c5251a98a9
|
feat(model_runner): remove pool/backend refs from ForwardBatch via ForwardContext (#25983)
Co-authored-by: Claude Sonnet 4.6 (1M context) <noreply@anthropic.com>
|
2026-05-21 14:01:49 -07:00 |
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Shangming Cai
|
fbebdd5105
|
[CI] Enable nixl disaggregation test for decode radix cache (#25990)
|
2026-05-21 19:29:24 +08:00 |
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