 Liangsheng Yin
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dc5f59c3a2
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[Refactor] Clarify DeepSeek V4 metadata names for V4.1 (#38947)
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2026-09-10 15:42:52 -07:00 |
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Pengyun Lin
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d076eec427
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[SM120] Use exact query-head widths for DeepSeek-V4 sparse MLA decode (#36655)
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2026-09-10 15:40:17 -07:00 |
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paulzhang-tmandQiaolin-Yu
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bb15be6d79
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[Spec] Stage Inkling MTP draft metadata before verify (#38169)
Co-authored-by: Qiaolin-Yu <liin1211@outlook.com>
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2026-09-10 15:32:19 -07:00 |
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paulzhang-tm
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a63efd9056
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[Spec] Support large MTP batches in short-convolution metadata (#38558)
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2026-09-10 15:13:17 -07:00 |
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fd7743e0e1
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[Sampling] Support sampling masks with overlap scheduling (#36631)
Co-authored-by: ByronHsu <ByronHsu@users.noreply.github.com>
Co-authored-by: root <root@slurm-h200-208-179.slurm-compute.tenant-slurm.svc.cluster.local>
Co-authored-by: Byron Hsu <byron+per@periodiclabs.ai>
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2026-09-10 14:52:44 -07:00 |
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YAMY
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55b45cb45a
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fix(qsa): dequantize FP8 cached prefixes in the sparse prefill kernels (#38855)
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2026-09-10 14:07:39 -07:00 |
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06dfe05d65
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[Deps] Raise smg-grpc-servicer floor to >=0.9.0 to unbreak SMG E2E CI (#38801)
Co-authored-by: Kangyan Zhou <kangyan.zhou@radixark.ai>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
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2026-09-10 13:55:36 -07:00 |
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a26273d668
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[AMD] Quantize the bf16 MTP draft experts online to MXFP4 for Qwen3.5 (#38748)
Co-authored-by: Zijie Chen <300606707+zijiecode@users.noreply.github.com>
Co-authored-by: jacky.cheng <yichiche@amd.com>
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2026-09-10 13:00:41 -07:00 |
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James
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209654c420
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[NPU][Hicache] Optimize HiCache L2 IO with Memfabric acc_offload (#38826)
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2026-09-11 00:23:36 +08:00 |
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Shuwen Wang
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19b83b4b9d
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[Radix Cache] Fix PureSWA tail release without insertion (#38349)
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2026-09-10 23:55:48 +08:00 |
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Shuwen Wang
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cc7e43ad22
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[HiCache] Account for newly pinned ancestors in load-back quota (#38481)
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2026-09-10 23:54:08 +08:00 |
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pllimax
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92dffebe16
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[NPU] Set DEEPEP_HYBRID_DEPLOYMENT for new DeepEP tests; switch glm5_2 to w8a8; tune nightly timeouts (#38775)
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2026-09-10 23:32:54 +08:00 |
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Chengze Fan
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12771786f2
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[AMD] Restore AITER verify runtime sizing reverted by #34647 (#38575)
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2026-09-10 05:57:47 -07:00 |
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Jialin Ouyang
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908226fea2
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[Rust TreeCore] Support external cache linker (#37306)
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2026-09-10 19:22:24 +08:00 |
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liupeng374
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334e94d8ac
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[NPU] fix pp 2 hang on npu (#38249)
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2026-09-10 19:21:37 +08:00 |
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Mohammad Miadh AngkadandMohammad Angkad
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dc2157dcd6
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[JIT] Port the expert-pack MXFP4 kernels to load_jit and fix their launch limits (#38830)
Co-authored-by: Mohammad Angkad <mohammad.angkad@radixark.ai>
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2026-09-10 17:50:51 +08:00 |
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MickandMick Qian
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c9c26d56b2
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[diffusion] docs: sync snapshot and minimax-h3 subblock features (#38784)
Co-authored-by: Mick Qian <mickqian@users.noreply.github.com>
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2026-09-10 17:23:43 +08:00 |
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8a6ab89bf0
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[AMD] Enable Fast Triton Sparse MLA backend (#30575)
Co-authored-by: clintg6 <7388379+clintg6@users.noreply.github.com>
Co-authored-by: HAI <hixiao@gmail.com>
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2026-09-10 01:58:00 -07:00 |
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ashwini rathi
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b23db06769
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pyproject(xpu): drop human-eval git dep to unblock image build (#38824)
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2026-09-10 16:24:43 +08:00 |
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1b77f498a0
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[NVIDIA] Support flashinfer Mega Moe (#31470)
Co-authored-by: djns99 <40156487+djns99@users.noreply.github.com>
Co-authored-by: 云挚 <ningyunxiao.nyx@antgroup.com>
Co-authored-by: Yangmin Li <yangminl@nvidia.com>
Co-authored-by: Po-Han Huang (NVIDIA) <53919306+nvpohanh@users.noreply.github.com>
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2026-09-10 00:22:47 -07:00 |
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Brayden ZhongandBrayden Zhong
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c0b790cf7f
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Delete cutlass_mla, non-Marlin GPTQ, AWQ AOT kernel, and Dual Chunk Flash Attention (#32114)
Co-authored-by: Brayden Zhong <brayden@radixark.ai>
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2026-09-10 15:12:01 +08:00 |
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Brayden ZhongandBrayden Zhong
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7152c14384
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Fix DeepSeek-V4 routing: sqrtsoftplus underflow and unfloored renorm (#34459)
Co-authored-by: Brayden Zhong <brayden@radixark.ai>
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2026-09-10 15:10:50 +08:00 |
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Shuwen Wang
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058cca0192
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[HiCache] Fix side pools to use resolved host allocator (#38350)
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2026-09-10 14:28:20 +08:00 |
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DAI0818andPo-Han Huang
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03e4c06589
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Fix Qwen3.5 GDN multi-item scoring (#33922)
Co-authored-by: Po-Han Huang (NVIDIA) <53919306+nvpohanh@users.noreply.github.com>
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2026-09-09 22:30:39 -07:00 |
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ashwini rathiandarathi-hlab
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6ab6df54b9
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Add missing test dependencies to pyproject.toml variants (#36098)
Co-authored-by: arathi-hlab <arathi.rajendran@intel.com>
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2026-09-10 12:49:16 +08:00 |
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Cheng Wan
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f1a512c51c
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[Config] msgspec.Struct for the config tier (#38753)
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2026-09-09 19:41:19 -07:00 |
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Cheng Wan
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53dc77ff4e
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[Config] One writer for the declaration stash; no exception to the write seal (#38752)
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2026-09-09 19:22:06 -07:00 |
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fd596a474c
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[XPU][Fix] Pack device-pointer tables as uint64 to avoid 64-bit address overflow (#35051)
Co-authored-by: roopaksrivastav <roopak.srivastava@intel.com>
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
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2026-09-10 10:12:18 +08:00 |
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Mick
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7f0285093e
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[diffusion] feat: spill large tensors over shared memory like numpy arrays (#38656)
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2026-09-10 09:14:06 +08:00 |
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MickandMick Qian
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ce555ed82a
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[diffusion] refactor: refactor utility ownership and document helper placement (#38699)
Co-authored-by: Mick Qian <mickqian@users.noreply.github.com>
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2026-09-10 09:11:01 +08:00 |
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LinyuanLi
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3ff226ba8f
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[NPU]Support GLM5.2 and FP8 DSA&Indexer kvcache for 950 (#38250)
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2026-09-10 09:10:10 +08:00 |
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92d831d3d7
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[AMD] Parallelize aiter spec-decode KV index building over token blocks (#37659)
Co-authored-by: Zijie Chen <300606707+zijiecode@users.noreply.github.com>
Co-authored-by: jacky.cheng <yichiche@amd.com>
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2026-09-09 17:53:53 -07:00 |
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880d6fa64d
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[DSv4] Integrate TRT-LLM DSv4 Attention for SM100/103 (#30805)
Co-authored-by: Yangmin Li <yangminl@nvidia.com>
Co-authored-by: Po-Han Huang (NVIDIA) <53919306+nvpohanh@users.noreply.github.com>
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2026-09-09 17:40:07 -07:00 |
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William Hu
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0084030179
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Add Opt-In for GLM-5.3 Flash breakable prefill CUDA graphs (#38522)
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2026-09-09 17:02:08 -07:00 |
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Po-Han Huang (NVIDIA)
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51c8581a26
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[Rust] Gate health on startup warmup completion (#37994)
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2026-09-09 15:55:13 -07:00 |
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Zhiqiang Xie
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beaf3d9252
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[HiCache] Replace skip_lock_node_ids with a segment lock protocol (#36848)
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2026-09-09 14:55:51 -07:00 |
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FrancisandQiaolin-Yu
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a84ffd1326
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feat: add optimized Domino rollout to DFlash V2 (#36899)
Co-authored-by: Qiaolin-Yu <liin1211@outlook.com>
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2026-09-09 14:12:15 -07:00 |
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Po-Han Huang (NVIDIA)andYAMY
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96d91ef926
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[Model] Support GLM-5.3 Flash NVFP4 loading (#38621)
Co-authored-by: YAMY <74099316+YAMY1234@users.noreply.github.com>
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2026-09-09 13:51:08 -07:00 |
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bede776c2a
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fix(unified-memory): evict Full KV for Mamba byte shortfalls (#36713)
Co-authored-by: Yangmin Li <yangminl@nvidia.com>
Co-authored-by: YAMY <74099316+YAMY1234@users.noreply.github.com>
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2026-09-09 13:46:51 -07:00 |
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paulzhang-tm
|
6c1d0b1b29
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Revert "[Spec] Publish the final multi-layer EAGLE shared-read event" (#38041)
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2026-09-09 13:01:16 -07:00 |
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Alison ShaoandClaude Opus 5
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95a88bfd69
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Relax GSM8K thresholds for the GLM-5.2 DSA-MTP variants (#38725)
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
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2026-09-09 12:46:10 -07:00 |
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cctry
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354ee46c26
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Keep VMM capability votes on CPU (#38722)
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2026-09-09 11:56:30 -07:00 |
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Sage
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8733da8cf4
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[rust-server] Use node-local HTTP ports for DP attention (#34430)
Signed-off-by: Sage Ahrac <sagiahrak@gmail.com>
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2026-09-10 02:22:44 +08:00 |
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7b791c9534
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[Bugfix] Keep a shared MAX_LEN prefill CUDA graph bucket when the graph captures a DP gather (MegaMoE sparse-DP hang) (#37933)
Co-authored-by: shyeh25 <206795756+shyeh25@users.noreply.github.com>
Co-authored-by: Po-Han Huang (NVIDIA) <53919306+nvpohanh@users.noreply.github.com>
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2026-09-09 10:52:16 -07:00 |
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0027af2eac
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[diffusion] [NPU] Optimize LTX-2/2.3 inference performance for NPU (#34722)
Co-authored-by: Elizaveta Martirosian <you@example.com>
Co-authored-by: ronnie_zheng <zl19940307@163.com>
Co-authored-by: root <root@localhost.localdomain>
Co-authored-by: Makcum888e <79456407+Makcum888e@users.noreply.github.com>
Co-authored-by: mickqian <mickqian@users.noreply.github.com>
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2026-09-09 19:36:18 +03:00 |
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HuangJi
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ffe98a4279
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[Diffusion][MiniMax-H3] Add SM90 Sage compute for SubBlock sparse attention (#37982)
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2026-09-09 20:00:03 +08:00 |
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Even Zhou
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dba34cc964
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[NPU] Bump memfabric and sgl-kernel-npu versions in docs and pyproject_npu.toml (#38437)
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2026-09-09 19:53:49 +08:00 |
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Mohammad Miadh AngkadandMohammad Angkad
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72d5c5bb73
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[Kimi-K3] Accept fp32 routing weights in the fused MoE finalize (#38612)
Co-authored-by: Mohammad Angkad <mohammad.angkad@radixark.ai>
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2026-09-09 01:33:39 -07:00 |
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ashwini rathiandarathi-hlab
|
d10ebdd0cb
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docker(xpu): unblock nightly build (setvars.sh + sgl-kernel rename) (#38617)
Co-authored-by: arathi-hlab <arathi-hlab@users.noreply.github.com>
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2026-09-09 16:32:16 +08:00 |
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YAMY
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1ad3eb09a9
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[Attention] Size FlashInfer MLA indptr buffers to the padded max batch (#38590)
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2026-09-09 01:25:29 -07:00 |
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