 Ziang Li
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dbd4302bbb
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Keep NVFP4 blockscale swizzle padding on the input device (#39141)
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2026-09-11 22:18:02 -07:00 |
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Aurick Qiao
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c389dd0863
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Fix RunAI object-storage checkpoint index filtering (#38988)
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2026-09-12 12:25:57 +08:00 |
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iridiumine
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a984c78330
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[NPU] Support DFlash speculative decoding for MiMo-V2.5-Pro (mxfp4) (#37565)
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2026-09-12 11:59:23 +08:00 |
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ff1ce11348
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[diffusion] model: support VDN-H3 with a hybrid_window_attn_h3 backend (#37903)
Co-authored-by: Claude Fable 5.1 <noreply@anthropic.com>
Co-authored-by: Haocheng Xi <xihc@berkeley.edu>
Co-authored-by: Mick <mickjagger19@icloud.com>
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2026-09-12 11:36:32 +08:00 |
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FrancisandQiaolin-Yu
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e91c948057
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feat: support TP>1 Domino rollout for DFlash V2 (#37069)
Co-authored-by: Qiaolin-Yu <liin1211@outlook.com>
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2026-09-11 18:51:11 -07:00 |
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Vignesh Sethuraman
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0d1bea77da
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[AMD] Allow aiter attention backend for Gemma-4 (#38758)
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2026-09-11 18:48:26 -07:00 |
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Vignesh Sethuraman
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e1d364dd1f
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[AMD] aiter: route head_dim>256 prefill through Triton unified_attention (#38757)
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2026-09-11 18:40:11 -07:00 |
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b805cc5014
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[Bugfix] Track DFlash Mamba state at checkpoint boundaries (#37818)
Co-authored-by: lvweiv <vwei.lv@gmail.com>
Co-authored-by: kpham-sgl <khoa.pham@radixark.ai>
Co-authored-by: Claude Fable 5.1 <noreply@anthropic.com>
Co-authored-by: Baizhou Zhang <sobereddiezhang@gmail.com>
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2026-09-11 18:38:09 -07:00 |
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a207786205
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[PD] Transfer the DCP-replicated DSPARK draft KV in DCP1->DCP-N relayouts (#37709)
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
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2026-09-11 17:15:18 -07:00 |
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7d9c57da6e
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[Session] Fix session idle timeout after rejected requests (#39035)
Co-authored-by: Byron Hsu <byron+per@periodiclabs.ai>
Co-authored-by: Manik Singhal <3400497+Manikvsin@users.noreply.github.com>
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2026-09-11 16:59:43 -07:00 |
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Xinyu Kang
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6671cfc775
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[AMD] Fix weight checking for AITER-shuffled block FP8 weights (#34330)
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2026-09-11 15:49:56 -07:00 |
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YAMY
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f963d7a27c
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fix(qsa): make the paged sparse-decode gather memory-safe (zero-fill scratch, int64 offsets, dequant FP8 on gather) (#38851)
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2026-09-11 15:47:25 -07:00 |
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Yanbin Jiang
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ec30f19e4a
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[LoRA] Support MoE in full and breakable prefill CUDA graphs (#38578)
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2026-09-11 14:40:02 -07:00 |
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Hanming Lu
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45715e7f20
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[Fix] Disable NCCL graph buffer registration for the TP LM-head all-to-all (pure-DP decode hang under request bursts) (#38936)
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2026-09-11 13:10:48 -07:00 |
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Bingxu Chen
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a338a9a01c
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[AMD][CI] Skip failing Wave test and relax multi-LoRA output check (#38585)
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2026-09-11 12:25:20 -07:00 |
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billishyahaoandHAI
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833bce9df5
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[AMD][DCP 1/N] add dcp support for aiter backend (#34432)
Co-authored-by: HAI <hixiao@gmail.com>
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2026-09-11 10:35:51 -07:00 |
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Jeremy Zhang
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f69d6fc28a
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[OpenAI] Propagate PD routing metadata through /v1/responses (#35503)
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2026-09-12 01:33:38 +08:00 |
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Vignesh Sethuraman
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ddf02a4f58
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[AMD] aiter: resolve SWA KV pool for draft workers + guard paged decode (#38756)
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2026-09-11 10:13:48 -07:00 |
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Xiaoyu Zhang
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d6b5dca90c
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[Diffusion] Optimize SANA-WM convolution post-processing and streaming GDN (#38529)
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2026-09-11 23:30:17 +08:00 |
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2a46cf2ca0
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[PD] Share the prefill->decode failure notification across backends (#36612)
Co-authored-by: inkcherry <mingzhi.liu@amd.com>
Co-authored-by: Shangming Cai <csmthu@gmail.com>
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2026-09-11 23:16:17 +08:00 |
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MickandMick Qian
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e016de462c
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[diffusion] CI: expose nightly server telemetry coverage (#38782)
Co-authored-by: Mick Qian <mickqian@users.noreply.github.com>
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2026-09-11 23:07:37 +08:00 |
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Xiaoyu Zhang
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7f09fbcd25
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[Diffusion] Preserve BF16 rounding in Hopper LTX QKNorm and RoPE fusion (#38533)
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2026-09-11 23:02:54 +08:00 |
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MickandMick Qian
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dd67a42634
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[diffusion] UX: quiet request-path cache diagnostics (#38783)
Co-authored-by: Mick Qian <mickqian@users.noreply.github.com>
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2026-09-11 22:45:21 +08:00 |
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593c7a900d
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Add granite_thinking_parser reasoning parser for Granite 4.2 (#38693)
Signed-off-by: Yousaf Shah <yousaf.shah@gmail.com>
Co-authored-by: Claude <noreply@anthropic.com>
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
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2026-09-11 07:18:35 -07:00 |
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335f6aab27
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[DSV4] Support raw-index output in TopK v2 (#33672)
Co-authored-by: weireweire <20922698+weireweire@users.noreply.github.com>
Co-authored-by: Brayden Zhong <b8zhong@uwaterloo.ca>
Co-authored-by: Po-Han Huang (NVIDIA) <53919306+nvpohanh@users.noreply.github.com>
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2026-09-11 07:17:36 -07:00 |
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MickandClaude Opus 5
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ab9750fb35
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[diffusion] optimization: pin layerwise host stores in place at their exact size (#39021)
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
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2026-09-11 22:04:40 +08:00 |
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Xinyuan Tong
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e8a36d339c
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Auto-detect GLM-5.3 chat templates as glm45/glm47 parsers (#38297)
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2026-09-11 09:02:44 -04:00 |
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MickandMick Qian
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358c163250
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[diffusion] fix: recover ipc jit initialization after interrupted builds (#39034)
Co-authored-by: Mick Qian <mickqian@users.noreply.github.com>
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2026-09-11 19:34:09 +08:00 |
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James
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165d8dd177
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[NPU][Hicache] Add Ascend Memcache Hicache L3 storage backend (#38827)
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2026-09-11 18:54:00 +08:00 |
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Liwansi
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747734dce4
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[NPU]glm5.2 fp8 memory opt (#38807)
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2026-09-11 18:48:45 +08:00 |
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822e73ccdd
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[Unified Cache][AMD] Support DeepSeek-V4 unified KV in direct external linkers (#38269)
Co-authored-by: amd-danli103 <danli103@amd.com>
Co-authored-by: Duyi-Wang <duyi.wang@amd.com>
Co-authored-by: TianDi101 <tiandi920722@gmail.com>
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2026-09-11 01:49:29 -07:00 |
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Liangsheng Yin
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17fa5ad327
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[Refactor] Generalize attention graph variants in the decode runner (#38993)
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2026-09-11 00:45:58 -07:00 |
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AMD-yanfeiwang
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69aa46b2fa
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[ROCm] Raise HiCache JIT block quota for mapped-host throughput (#39036)
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2026-09-11 00:12:24 -07:00 |
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Shuwen Wang
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a713349faf
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[HiCache] fix: preserve SWA host lock boundaries across splits (#38835)
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2026-09-11 14:58:26 +08:00 |
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Vignesh Sethuraman
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76ef679cb1
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[AMD] aiter: fail loudly on cross-layer KV sharing in target_verify (#38755)
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2026-09-10 23:37:03 -07:00 |
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Bingxu Chen
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2465ee3948
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[AMD] Fix DeepSeek block-FP8 loading on gfx94x (#38446)
Signed-off-by: Bingxu Chen <bingxche@amd.com>
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2026-09-10 23:00:29 -07:00 |
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Shunkangz
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40a84d6dfc
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[kv-shard 1/4] Logical-page placement with UnifiedRadixCache (#38356)
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2026-09-10 22:06:42 -07:00 |
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Liangsheng Yin
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94ce940ff8
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[Bug] Include DSA variant in exact-bucket graph admission (#38992)
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2026-09-10 21:03:03 -07:00 |
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yuchengliu1andMa Mingfei
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480b14edad
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[xpu] install xpu-kernel by released wheel (#37394)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
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2026-09-11 10:47:27 +08:00 |
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ANSHUMAN TRIPATHYandMa Mingfei
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0fadad8933
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DFLASH support added for XPU (#32798)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
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2026-09-11 10:39:37 +08:00 |
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Miaomiao Jiang
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690428b470
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[XPU] Add xpu forward in Gemma3RMSNorm & Add test and benchmark for Gemma3RMSNorm (#36278)
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2026-09-11 10:32:25 +08:00 |
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Vignesh Sethuraman
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7e3ae15f73
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[AMD] aiter: honor per-layer softmax scale (#38754)
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2026-09-10 19:27:09 -07:00 |
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ANSHUMAN TRIPATHY
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3716e496ea
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Speculative Decoding support for intel_xpu attention backend on XPU target (#30548)
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2026-09-11 10:25:25 +08:00 |
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ANSHUMAN TRIPATHYandmingfeima
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2adb2e8485
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[XPU] Adapt device agnostic API usage (#32093)
Co-authored-by: mingfeima <mingfei.ma@intel.com>
|
2026-09-11 10:03:12 +08:00 |
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Siju Samuel
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67d3a2ea57
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[XPU] Make checkpoint_engine worker device-agnostic (#32382)
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2026-09-11 09:56:39 +08:00 |
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ad7f57c9ea
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[Responses] Fix empty-prompt routing for token-first chat encoders (kimi_k3, inkling) (#35486)
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
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2026-09-11 01:06:20 +00:00 |
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jasonjk-park
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9df72e8f5a
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Fix custom logit processor params when num_tokens_in_batch is used (#38730)
|
2026-09-10 17:52:08 -07:00 |
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Alexandrandronnie_zheng
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d0035da34e
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[Diffusion][Refactor] Refactor and unify RoPE execution for DiT models using RotaryEmbedding based on CustomOp (#33555)
Co-authored-by: ronnie_zheng <zl19940307@163.com>
|
2026-09-11 08:31:05 +08:00 |
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Liangsheng Yin
|
41da06adca
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[Refactor] Generalize DeepSeek V4 compressed pool management (#38954)
|
2026-09-10 17:29:03 -07:00 |
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Mohammad Miadh AngkadandMohammad Angkad
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52c191da52
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[Deps] Retire the CUDA 12 lane (#38404)
Co-authored-by: Mohammad Angkad <mohammad.angkad@radixark.ai>
|
2026-09-10 16:58:09 -07:00 |
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