 MingxuZh
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21ba329dac
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[Xeon] CPU CI enhancement for Intel Xeon platforms (#24649)
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2026-05-28 10:49:04 +08:00 |
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Liangsheng Yin
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b7d62bd724
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[CI] Rename basic CI stage-a/b/c -> base-a/b/c for symmetry with extra CI (#25420)
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2026-05-15 18:26:55 -07:00 |
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sglang-botandsglang-bot
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da175b964d
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chore: update CI test est_time values (#23785)
Co-authored-by: sglang-bot <sglang-bot@users.noreply.github.com>
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2026-04-26 20:17:50 -07:00 |
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265696b176
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chore: update CI test est_time values (#22565)
Co-authored-by: Cheng Wan <chwan@rice.edu>
Co-authored-by: sglang-bot <sglang-bot@users.noreply.github.com>
Co-authored-by: Cheng Wan <54331508+ch-wan@users.noreply.github.com>
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2026-04-10 18:15:02 -07:00 |
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Liangsheng YinandClaude Opus 4.6
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875a615993
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fix(ci): update est_time for 57 tests based on runtime analysis (#21896)
Co-authored-by: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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2026-04-01 20:16:13 -07:00 |
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Lianmin Zheng
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814202704b
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ci: unify PR test suite naming (#21187)
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2026-03-23 00:18:45 -07:00 |
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Liangsheng Yin
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f0458e0b49
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[Utils] Move network/socket utilities from common.py to network.py (#20646)
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2026-03-15 20:35:24 -07:00 |
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Liangsheng Yin
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d852f26cb6
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Fix dual-stack socket handling: IPV6_V6ONLY, IPv4-first, is_port_available all-family check (#20643)
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2026-03-15 17:17:23 -07:00 |
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psaabandhnyls2002
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1145805e7d
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Fix socket utilities and reserve_port for IPv6 dual-stack support (#20491)
Co-authored-by: hnyls2002 <lsyincs@gmail.com>
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2026-03-15 14:29:10 -07:00 |
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