 cctryandcctry
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0c065671c9
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[Spec] Redo: split init_backends; account draft weights in --mem-fraction-static (#28855)
Co-authored-by: cctry <cctry@fb.com>
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2026-06-21 20:45:16 -07:00 |
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Vladislav Nosivskoy
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2ad9a5b576
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[UnifiedTree] Use dense model for HiCache+CP KL tests (#28726)
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2026-06-20 00:18:01 +08:00 |
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huangtingweiandhzh0425
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6b7ecca663
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[HiCache]Support hybrid pool staged H2D kernel (#28434)
Co-authored-by: hzh0425 <hzh0425@apache.org>
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2026-06-19 09:48:03 +08:00 |
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Zhanghengandispobock
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867707f1f2
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[UnifiedTree]: move some kl test from base to extra stage (#28627)
Co-authored-by: ispobock <ispobaoke@gmail.com>
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2026-06-18 01:39:46 -07:00 |
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Vladislav NosivskoyandZhangheng
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b7ae7149e8
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[HiCache] Fix SWA L3 cache miss due to a prefetch/hit len mismatch (#27291)
Co-authored-by: Zhangheng <hzh0425@apache.org>
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2026-06-18 14:55:00 +08:00 |
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Yuan Luoandluoyuan.luo
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3340f4e3da
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[GDN][KDA][mem_cache] int8 checkpoint pool for the linear-attn prefix cache (#28185)
Co-authored-by: luoyuan.luo <luoyuan.luo@antgroup.com>
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2026-06-17 20:41:46 -07:00 |
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Michael
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a2aa51c818
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[AMD] register 4 2-gpu tests to stage-b-test-2-gpu-large-amd (#28344)
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2026-06-16 21:58:34 -07:00 |
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Chao Shi
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5fb4e2d02e
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[UnifiedTree] Use Qwen3-32B in unified radix pp kl tests and set KL threshold to 0.005 (#27931)
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2026-06-14 13:15:35 +08:00 |
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2495c02c2c
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[Refactor] Cuda Graph Runner/Backend Refactor (#23906)
Co-authored-by: BBuf <1182563586@qq.com>
Co-authored-by: Cheng Wan <54331508+ch-wan@users.noreply.github.com>
Co-authored-by: Lianmin Zheng <lianminzheng@gmail.com>
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2026-06-09 21:36:57 -07:00 |
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huangtingwei
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f101b287ef
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[Unified Tree]fix compatibility with eagle key and l3 hicache (#27655)
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2026-06-10 10:54:45 +08:00 |
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Ke Bao
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854d232a40
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Fix flaky hicache l3 mmlu nightly test (#27688)
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2026-06-10 10:01:14 +08:00 |
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Zhangheng
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a39c428d3f
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[UnifiedTree][CI]: Reduce HiCache PP KL test concurrency to avoid decode OOM (#27483)
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2026-06-07 17:12:42 +08:00 |
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42fe025280
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[HiCache] Fix the compatibility between PP and HiCache (L2). (#27285)
Co-authored-by: ybyang <ybyang7@iflytek.com>
Co-authored-by: hzh0425 <hzh0425@apache.org>
Co-authored-by: shangmingc <csmthu@gmail.com>
Co-authored-by: 晟海 <huangtingwei.htw@antgroup.com>
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2026-06-06 16:57:23 +08:00 |
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Zhangheng
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631db6c757
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[UnifiedTree]: Sync sidecar component hits across TP ranks and make SWA prefetch all-or-nothing (#27264)
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2026-06-05 09:23:54 +08:00 |
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Vladislav NosivskoyandZhangheng
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63dc20ae6c
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[UnifiedTree] Add CP sync (#25395)
Co-authored-by: Zhangheng <hzh0425@apache.org>
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2026-06-03 16:10:27 +08:00 |
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Ke Bao
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28f9c1ff24
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Relax mamba unified cache kl threshold (#27070)
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2026-06-02 23:28:22 +08:00 |
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Ke Bao
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b5e154dc73
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Fix stale import after kl_nightly rename (#27064)
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2026-06-02 21:46:21 +08:00 |
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Zhangheng
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ee4bf0a9d3
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[UnifiedTree]: Add HiCache Nightly CI For GLM5 (#26927)
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2026-06-02 19:02:50 +08:00 |
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Zhangheng
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eb5d4827e8
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[UnifiedTree]: Split unified tree kl ci into multiple files to reduce GPU usage. (#26666)
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2026-05-29 02:46:34 -07:00 |
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Liangsheng Yin
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ec78fa6518
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test/registered: cleanup pure model e2e tests (moves, splits, dedup, kit) (#26610)
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2026-05-28 15:41:46 -07:00 |
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Zhangheng
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38f32c38ab
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[UnifiedRadixTree]: Support L3 HiStorage framework (#26062)
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2026-05-26 22:38:00 +08:00 |
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Liangsheng Yin
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614672fea5
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[Test] Stage-a sanity kits; consolidate core/ + models_e2e/ tests (#25831)
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2026-05-20 01:58:48 -07:00 |
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huangtingweiandhzh0425
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c2a212bfe2
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[UnifiedTree] Support DeepSeek V4 host pool with multiple layouts. (#25282)
Co-authored-by: hzh0425 <hzh0425@apache.org>
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2026-05-19 09:36:00 +08:00 |
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Cheng Wan
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b7267e8fce
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[CI] Enable weight prefetch for 8-gpu-h200 basic tests (#25684)
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2026-05-18 14:12:45 -07:00 |
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Cheng Wan
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0c017db916
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Update kl_div_thres to 0.02 in swa_radix_cache (#25497)
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2026-05-16 16:43:12 -07:00 |
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Zhangheng
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0be539024f
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[BugFix]: Fix DeepSeek V4 HiCache layer count logic (#25477)
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2026-05-16 23:50:01 +08:00 |
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Liangsheng Yin
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b7d62bd724
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[CI] Rename basic CI stage-a/b/c -> base-a/b/c for symmetry with extra CI (#25420)
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2026-05-15 18:26:55 -07:00 |
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Zhangheng
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21b3ac52b4
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[UnifiedTree]: Fix UnifiedRadixCache device match semantics with HiCache (#25277)
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2026-05-16 00:40:55 +08:00 |
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Zhangheng
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fe7a5dd3bf
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[UnifiedTree]: Add nightly hicache ci for dsa model (#25348)
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2026-05-15 16:54:50 +08:00 |
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d9fa84b25b
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[UnifiedTree]: Support HiCache For DeepSeek_V4 (#24691)
Co-authored-by: ispobock <ispobaoke@gmail.com>
Co-authored-by: 晟海 <huangtingwei.htw@antgroup.com>
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2026-05-14 20:20:52 -07:00 |
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Liangsheng Yin
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22d3f3996c
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ci: decouple stage and runner for cuda registry (#25197)
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2026-05-13 17:28:21 -07:00 |
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Michael
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245f7d8026
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[AMD] Register 5 server-style 1-GPU tests for AMD PR CI (#24572)
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2026-05-12 22:45:52 -07:00 |
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Zhangheng
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e299ec1bff
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[UnifiedRadixTree]: Fix flaky ci (#24421)
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2026-05-05 20:22:19 +08:00 |
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Zhangheng
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05aed5e1d5
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[UnifiedRadixTree]: Add KL accuracy CI for UnifiedTree with HiCache (#24346)
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2026-05-04 20:18:10 +08:00 |
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c0f5950636
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[UnifiedRadixTree]: Support HiCache Framework for UnifiedRadixTree (#23316)
Co-authored-by: JINZ <1023553676@qq.com>
Co-authored-by: diemchai <diemchai@tencent.com>
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2026-05-03 22:13:22 +08:00 |
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sglang-botandsglang-bot
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da175b964d
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chore: update CI test est_time values (#23785)
Co-authored-by: sglang-bot <sglang-bot@users.noreply.github.com>
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2026-04-26 20:17:50 -07:00 |
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bc59cc0f96
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[RaidxTree Refactor]: Support Unified HybridRadixTree V2 (#21206)
Co-authored-by: ispobock <ispobaoke@gmail.com>
Co-authored-by: pansicheng <sicheng.pan.chn@gmail.com>
Co-authored-by: yizhang2077 <1109276519@qq.com>
Co-authored-by: xiezhq-hermann <xiezhq@stanford.edu>
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2026-04-13 10:28:22 +08:00 |
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265696b176
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chore: update CI test est_time values (#22565)
Co-authored-by: Cheng Wan <chwan@rice.edu>
Co-authored-by: sglang-bot <sglang-bot@users.noreply.github.com>
Co-authored-by: Cheng Wan <54331508+ch-wan@users.noreply.github.com>
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2026-04-10 18:15:02 -07:00 |
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Lianmin Zheng
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814202704b
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ci: unify PR test suite naming (#21187)
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2026-03-23 00:18:45 -07:00 |
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Ke Bao
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c3483e8e97
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[CI] Move existing unit tests into unit directory (#20631)
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2026-03-15 23:25:18 +08:00 |
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hzh0425
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197f807134
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[RadixTree][7/N Refactor]: Refactor mamba radix tree, release dup kvcache in insert func (#19429)
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2026-03-13 12:28:32 +08:00 |
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roikoren755
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067353f67b
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[Test] Refactor KL divergence and prefix cache branching to kits (#19715)
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2026-03-12 16:11:59 +08:00 |
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liubiyonggeandzhangheng
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cc73355a1f
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[Feature] Add SLRU eviction policy & fix RadixCache hit_count bug (#18843)
Co-authored-by: zhangheng <hzh0425@apache.org>
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2026-03-08 21:30:55 +08:00 |
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Yuwei An
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c64274c746
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Piecewise Cuda Graph set default (#16331)
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2026-03-02 23:18:07 +08:00 |
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zhangheng
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a0d8a7ae6d
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[RadixTree][6/N Refactor]: Refactor SWARadixTree to simplify the computation and alignment of bigram keys. (#19427)
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2026-02-28 20:01:39 +08:00 |
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pansicheng
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48642d5384
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[RadixTree][4/N Refactor]: Move available_and_evictable_str to individual radix cache classes (#17852)
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2026-02-19 17:03:15 +08:00 |
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Liangsheng Yin
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cd90346a2b
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Add cache hit rate UT (#18566)
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2026-02-10 21:27:41 -08:00 |
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495290aefd
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enable ut test for xpu devices (#11712)
Co-authored-by: jundu <jun.du@intel.com>
Co-authored-by: Gao, Pengfei <pengfei.gao@intel.com>
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2026-02-03 11:15:14 -08:00 |
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cctry
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027f314050
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[Fix] data race in req_to_token pool (#17850)
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2026-02-02 14:38:15 -08:00 |
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Ke Bao
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7ace64d1d8
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Update mamba env setting (#17566)
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2026-01-23 11:02:32 +08:00 |
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