 MingxuZh
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21ba329dac
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[Xeon] CPU CI enhancement for Intel Xeon platforms (#24649)
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2026-05-28 10:49:04 +08:00 |
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Liangsheng Yin
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b7d62bd724
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[CI] Rename basic CI stage-a/b/c -> base-a/b/c for symmetry with extra CI (#25420)
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2026-05-15 18:26:55 -07:00 |
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Lianmin Zheng
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814202704b
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ci: unify PR test suite naming (#21187)
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2026-03-23 00:18:45 -07:00 |
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Lianmin Zheng
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cea79530f8
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ci: merge CPU default and stage-a-cpu-only suites (#20992)
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2026-03-20 00:04:55 -07:00 |
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fzyzcjy
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d7aa0ce72f
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Support multiple engines for router simulation in schedule simulator (#16368)
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2026-01-04 11:46:05 +08:00 |
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fzyzcjy
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24e116ef6a
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Enhance schedule simulator and add several e2e scenarios (#16357)
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2026-01-04 10:02:38 +08:00 |
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fzyzcjy
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8ca9597057
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Tiny support sticky routing algorithm in schedule simulator (#16355)
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2026-01-04 08:36:52 +08:00 |
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fzyzcjy
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ef5ac6f01e
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Support shared prefix (gsp) in schedule simulator (#16353)
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2026-01-04 08:03:16 +08:00 |
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fzyzcjy
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e139d2aa76
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Super tiny fix CI (#16351)
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2026-01-04 07:24:46 +08:00 |
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fzyzcjy
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87ef05e2e1
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Support simple schedule simulator (#16344)
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2026-01-03 22:05:40 +08:00 |
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