 Ke Bao
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d528192bf9
|
Skip inkling sheared bias under batch invariance (#35161)
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2026-08-18 12:22:58 +08:00 |
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amd-danli103andThomas Wang
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d01812d89e
|
[AMD] Optimize KIMI-K3 with Triton MLA decode kernel by tuning the stage-1 geometry for gfx950 (#34580)
Co-authored-by: Thomas Wang <thomawan@amd.com>
|
2026-08-17 21:16:14 -07:00 |
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Khoa PhamandClaude Opus 5
|
f44a130c5e
|
[DCP] Drop the prefill index-selection syncs by taking each rank's rows by stride (#35084)
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
|
2026-08-17 19:55:51 -07:00 |
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Siyuan Chen
|
fcdaaf8a5d
|
[Feature] Optimize TP LMHead with All-to-All (#32313)
|
2026-08-17 19:55:27 -07:00 |
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jiayisunxandMa Mingfei
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d6c837489a
|
[XPU] Enable fused GDN QKV split Triton kernel on XPU (#30144)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
|
2026-08-18 10:42:58 +08:00 |
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MickandYiqi Yang
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d55f1c28e2
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[diffusion] feat: load quantized H3 text encoder checkpoints (#34986)
Co-authored-by: Yiqi Yang <yangyiqi8787@gmail.com>
|
2026-08-18 09:10:54 +08:00 |
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Liangsheng Yin
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c0b6474b43
|
[Spec] Reduce host-side overhead in ngram draft prep (#35207)
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2026-08-17 16:40:06 -07:00 |
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Cheng Wan
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b3c8f0d923
|
config: one control-plane log for the process (#35028)
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2026-08-17 16:19:00 -07:00 |
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Cheng Wan
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c70c7d72a8
|
config: the readback and the resolving view say what they are (#35027)
|
2026-08-17 16:18:19 -07:00 |
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Cheng Wan
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cba3c5d5ac
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config: the per-instance families read the bags (#35026)
|
2026-08-17 16:17:53 -07:00 |
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Cheng Wan
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a97bc8db32
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config: the DP/EP topology reads come from the parallel bag (#35025)
|
2026-08-17 16:17:26 -07:00 |
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Cheng Wan
|
d2bc697396
|
spec: size the speculative buffers from the bags, not the startup record (#35024)
|
2026-08-17 16:16:56 -07:00 |
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Cheng Wan
|
3d7ec00179
|
config: publish before a process reads configuration (#35023)
|
2026-08-17 16:16:20 -07:00 |
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Cheng Wan
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2b278b4ac4
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config: retire the multi-engine accommodation in the runtime context (#35022)
|
2026-08-17 16:15:33 -07:00 |
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|
Baizhou Zhang
|
bc312d185d
|
Clean deprecated DeepSeek V4 Environs (#34926)
|
2026-08-17 16:07:00 -07:00 |
|
|
Lennox Fu
|
b42abbb1ba
|
[metrics] Fix prefill FLOPs estimate to count prefix and per-request causal pairs (#34316)
|
2026-08-17 15:18:54 -07:00 |
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Lianmin Zheng
|
198a7b2fc9
|
[Misc] Clean up python/sglang package structure (#35062)
|
2026-08-17 14:24:35 -07:00 |
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|
Liangsheng Yin
|
032fe9c891
|
[Spec] Relay ngram accept tokens through the FutureMap (#35198)
|
2026-08-17 14:21:07 -07:00 |
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|
cctryandcctry
|
2e7c85da68
|
[PD] Preserve decode KV across retraction in HiCache (#34801)
Co-authored-by: cctry <cctry@fb.com>
|
2026-08-17 08:49:11 -07:00 |
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|
Lianmin Zheng
|
af743371cc
|
Clean up environ.py: remove dead env vars, unify deprecation handling, move examples to a unit test (#35060)
|
2026-08-17 06:53:34 -07:00 |
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|
Mick
|
d97b796c16
|
[diffusion] chore: reuse SRT CLIP encoder blocks (#35004)
|
2026-08-17 19:51:51 +08:00 |
|
|
Mick
|
e9ad8102a2
|
[diffusion] chore: reuse SRT SigLIP in Pi0.5 (#34992)
|
2026-08-17 19:33:36 +08:00 |
|
|
WenhaoZhang
|
f33b83b4cc
|
[diffusion] fix: fix h3 swap peft SwiGLU lora_B halves when loading FFN Lora (#34940)
|
2026-08-17 18:47:31 +08:00 |
|
|
Mohammad Miadh Angkad
|
82995a001b
|
Stabilize GB300 nightly tests (#35044)
|
2026-08-17 03:30:16 -07:00 |
|
|
|
744740dbea
|
[XPU] upgrade sglang xpu backend to PyTorch 2.13 (#31751)
Co-authored-by: MingxuZh <109504044+MingxuZh@users.noreply.github.com>
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
|
2026-08-17 18:29:15 +08:00 |
|
|
kangwangamd
|
c82e928fe5
|
[AMD] diffusion: normalize ModelOpt-FP8 weights to e4m3fnuz on gfx942 (#35111)
|
2026-08-17 02:35:10 -07:00 |
|
|
Alan Kao
|
056808723e
|
[AMD] Guard ROCm 7.0 build from using hipMemcpyBatchAsync (#35128)
|
2026-08-17 02:22:58 -07:00 |
|
|
|
92bce3d7bb
|
[AMD] [GLM5] fp8 MLA absorbed bmm for GLM-5.2 on gfx950 (#30519)
Co-authored-by: Thomas Wang <thomawan@amd.com>
Co-authored-by: sogalin_codegen <39478626+sogalin@users.noreply.github.com>
|
2026-08-17 02:15:16 -07:00 |
|
|
|
8cc112d486
|
[DSA] Skip indexer KV cache for skip-topk layers (#30531)
Co-authored-by: Brayden Zhong <brayden@radixark.ai>
Co-authored-by: mmangkad <mohammad.angkad@radixark.ai>
|
2026-08-17 02:02:23 -07:00 |
|
|
YAMY
|
7c423cfd41
|
[PD] Avoid unused PREBUILT prompt tensor transfer (#35070)
|
2026-08-17 16:48:12 +08:00 |
|
|
Liangsheng Yin
|
711bdacb82
|
[Spec] Resolve shared-read ends from the backend declaration alone (#35059)
|
2026-08-17 01:35:29 -07:00 |
|
|
|
b83d507cd7
|
[NPU] Support DeepSeek-V4 DSpark and refactor DSV4 cache management (#33676)
Co-authored-by: JiaruiChang5268 <jc5268@columbia.edu>
Co-authored-by: Kelon <kelonlu@163.com>
Co-authored-by: unknown <z8ruev42yk@gmail.com>
Co-authored-by: Talantan1102 <545811257@qq.com>
Co-authored-by: Talantan1102 <44429302+Talantan1102@users.noreply.github.com>
|
2026-08-17 16:27:44 +08:00 |
|
|
Ke Bao
|
4cad864361
|
Fix sconv track refresh on graph capture (#35042)
|
2026-08-17 15:51:45 +08:00 |
|
|
Mohammad Miadh AngkadandMohammad Angkad
|
5769b6d637
|
[JIT Kernel] Migrate causal_conv1d_fwd and causal_conv1d_update from AOT to JIT (#35031)
Co-authored-by: Mohammad Angkad <mohammad.angkad@radixark.ai>
|
2026-08-17 15:22:37 +08:00 |
|
|
Liangsheng Yin
|
0d8c850a35
|
[Fix] Read the DSA prefill CP flag from the parallel config bag in bootstrap (#35110)
|
2026-08-17 00:21:41 -07:00 |
|
|
Mohammad Miadh Angkad
|
721e359ca7
|
Suppress expected FlashInfer TRT-LLM workspace warnings (#34921)
|
2026-08-17 15:16:16 +08:00 |
|
|
Lianmin Zhengandwangwenchen0407
|
12a455a910
|
Fix world-size-one aliasing in MLP batch sync (#34997)
Co-authored-by: wangwenchen0407 <wangwenchen@meta.com>
|
2026-08-17 00:04:09 -07:00 |
|
|
vikram singh shekhawatandClaude Sonnet 4.5
|
f7a404e9c3
|
Fix rope config compatibility and VL/transformers-fallback weight loading (#31575)
Co-authored-by: Claude Sonnet 4.5 (1M context) <noreply@anthropic.com>
|
2026-08-17 14:53:59 +08:00 |
|
|
Liangsheng Yin
|
0099107e8b
|
Revert "[AMD] [GLM5] Fuse shared-expert append into aiter grouped-topk (skip per-layer append kernel)" (#35105)
|
2026-08-16 23:49:49 -07:00 |
|
|
ziang663andZhangheng
|
43226af812
|
fix(hicache): limit load-back pending to write-back (#34519)
Co-authored-by: Zhangheng <hzh0425@apache.org>
|
2026-08-17 14:23:54 +08:00 |
|
|
Lianmin ZhengandJialin Ouyang
|
9be3044b9c
|
[Engine] Freeze GC after server warmup (#34999)
Co-authored-by: Jialin Ouyang <Jialin.Ouyang@gmail.com>
|
2026-08-16 22:41:36 -07:00 |
|
|
Wang, FangYuan
|
eb61cb2823
|
[AMD] Support prefill context parallel two batch overlap for DeepSeek V4 (#33480)
|
2026-08-16 22:40:29 -07:00 |
|
|
Kaixi
|
f3225bceb3
|
[DSV4] Emit TMA-aligned UE8M0 scales for FP8 einsum (#34277)
|
2026-08-16 22:06:41 -07:00 |
|
|
Khoa PhamandClaude Opus 5
|
0fb040cbeb
|
[DCP]Localize HiCache DCP indices once per transfer, not per layer (#34889)
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
|
2026-08-16 21:54:51 -07:00 |
|
|
Enrique Shockwave
|
92b1d382c7
|
[Fix] Correct dense FP8 Marlin bias ordering (#35020)
|
2026-08-17 03:43:36 +00:00 |
|
|
|
b6d7602914
|
[CPU] Add support for Gemma4 on Xeon (#22498)
Co-authored-by: Copilot <198982749+Copilot@users.noreply.github.com>
Co-authored-by: jianan-gu <jianan.gu@intel.com>
Co-authored-by: Haotong Zou <haotong.zou@intel.com>
|
2026-08-17 10:52:26 +08:00 |
|
|
TobyMint
|
3adc70bb5e
|
[MoE] Add H20 fp8_w8a8 tuned configs for Qwen3.8 (triton 3.7.1) + fix Qwen3_5MoeForCausalLM tuning (#34795)
|
2026-08-16 19:41:03 -07:00 |
|
|
|
8e0499bd50
|
[AMD] [GLM5] Fuse shared-expert append into aiter grouped-topk (skip per-layer append kernel) (#31323)
Co-authored-by: Thomas Wang <thomawan@amd.com>
Co-authored-by: HaiShaw <hixiao@gmail.com>
|
2026-08-16 18:22:26 -07:00 |
|
|
Mick
|
0e178c3d22
|
[diffusion] chore: reuse srt siglip vision model (#34988)
|
2026-08-17 09:16:17 +08:00 |
|
|
Xiaoyu Zhang
|
0aa09ab40d
|
[diffusion] Reuse bit-exact modulation fast path for LTX-2.3 (#34930)
|
2026-08-17 09:04:10 +08:00 |
|