 Liangsheng Yin
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711bdacb82
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[Spec] Resolve shared-read ends from the backend declaration alone (#35059)
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2026-08-17 01:35:29 -07:00 |
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Liangsheng Yin
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bae353ba55
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[misc] Rename shared-read boundary to shared-read ends and fix wrapper delegation (#34982)
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2026-08-16 14:36:31 -07:00 |
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Liangsheng Yin
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0f7aaceda5
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[misc] Rename the WAR read-done fastpath to shared-read-done (#34916)
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2026-08-15 15:02:02 -07:00 |
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Liangsheng Yin
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a1ca76b24b
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[Scheduler] Unify WAR read-done gating behind shared-read boundary declarations (#34052)
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2026-08-08 03:26:36 -07:00 |
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f8f2870a84
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Profiling Enhancements [1/3]: cuda graph profile traces (#24370)
Co-authored-by: Basit <mohbasit@ctr2-alola-ctrl-01.amd.com>
Co-authored-by: HAI <hixiao@gmail.com>
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2026-08-06 03:19:35 -07:00 |
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Jialin Ouyang
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717a559f02
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[Scheduler] Align WAR fences with CUDA graph metadata reads (#33587)
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2026-08-05 13:52:20 -07:00 |
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Tao Liandlitao.dream
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a0b7bcf592
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[Feature] Support return_hidden_states="last" (#30177)
Co-authored-by: litao.dream <litao.dream@bytedance.com>
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2026-08-02 15:09:33 +08:00 |
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Yuwei AnandClaude Fable 5
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3e0f7c3f30
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[BCG][3/N] Enable bcg on dsa & deepep a2a backend (#31987)
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
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2026-07-31 16:45:18 -07:00 |
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paulzhang-tmandClaude Fable 5
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4e5a05148a
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[FullCG] Support chunked cached-prefix prefill (#30825)
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
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2026-07-28 11:20:25 -07:00 |
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Ethan (Yusheng) Su
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ee1736f39a
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[LoRA] Support LoRA under the breakable/full prefill CUDA graph (#30988)
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2026-07-26 22:10:03 -07:00 |
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Mick
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573c075fef
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CI: synchronize prefill graph test fixtures (#31665)
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2026-07-18 18:48:05 +08:00 |
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Mick
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6c6175fabd
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perf: avoid excessive prefill CUDA graph padding (#31487)
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2026-07-18 16:25:30 +08:00 |
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