 Ma Mingfei
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486a56be56
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[CPU] improve silu performance by replacing fp32 div with rcp14 (#31304)
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2026-07-17 12:02:37 +08:00 |
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Ma Mingfei
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bd3b252e0a
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[CPU] use faster exp in silu_and_mul (#29382)
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2026-06-29 09:38:30 +08:00 |
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Ma Mingfei
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3217410cf6
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[CPU] enable fused_sigmoid_mul on CPU device (#29378)
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2026-06-29 09:38:04 +08:00 |
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Ma Mingfei
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23e4d381f0
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[CPU] remove RECORD_FUNCTION (#23528)
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2026-04-24 09:18:29 +08:00 |
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blzheng
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d1d4074c4e
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[CPU] Add gelu_and_mul kernel in sgl-kernel and add ut (#9300)
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2025-09-08 23:23:13 -07:00 |
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a73c4df438
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Add optimized native kernels in sgl-kernel (#5150)
Co-authored-by: Chunyuan WU <chunyuan.wu@intel.com>
Co-authored-by: YanbingJiang <yanbing.jiang@intel.com>
Co-authored-by: blzheng <beilei.zheng@intel.com>
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2025-04-08 09:37:46 -07:00 |
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