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11391 Commits
Author SHA1 Message Date
zijiecjacky.chengYC Yen-Ching Tseng
 		ba1d980b35 [AMD] Accelerate AITER unified-attention decode with scaled FP8 Q (#31856) 
Co-authored-by: jacky.cheng <yichiche@amd.com>
Co-authored-by: YC Yen-Ching Tseng <yctseng@amd.com>
 2026-08-13 23:42:25 -07:00
Mick 46d84f4b48 feat(cli): add extensible serve backend plugins (#34753) 2026-08-14 13:57:59 +08:00
DarkSharpnessClaudeBBuf
 		b784726863 [kernel] Content-addressed JIT build cache, generated from our own ninja (#34274) 
Co-authored-by: Claude <noreply@anthropic.com>
Co-authored-by: BBuf <1182563586@qq.com>
 2026-08-14 13:41:04 +08:00
jacky.chengandsogalin_codegen 240a12b302 [AMD] Fuse shared_expert_gate GEMV into the MoE append kernel (HIP/aiter) (#28666) 
Co-authored-by: sogalin_codegen <39478626+sogalin@users.noreply.github.com>
 2026-08-13 21:32:27 -07:00
Baizhou Zhang 0a6bbbe128 [Fix] Restore layer-level DSV4 RoPE policy (#34788) 2026-08-13 21:26:45 -07:00
Runkai TaorunkaiXiaoyu Zhang
 		e1c4db9621 [quantization] Add tuned Triton tile configs for channelwise FP8 GEMM… (#34331) 
Co-authored-by: runkai <runkai@amazon.com>
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
 2026-08-14 11:11:02 +08:00
Xinyuan Tongandhnyls2002 85cdf1178d [CI] Prune redundant CPU test overhead (#34309) 
Co-authored-by: hnyls2002 <lsyincs@gmail.com>
 2026-08-13 19:51:17 -07:00
SII-yangdianandSII-yangdian f2b2b567aa perf(jit_kernel/deepseek_v4): optimize paged_mqa_metadata (#25855) 
Co-authored-by: SII-yangdian <yangdian@sii.edu.cn>
 2026-08-13 19:00:22 -07:00
Xiaoyu ZhangandClaude Fable 5 704e512836 [GDN] Honor configured linear-attn verify backend in the kernel dispatcher (#34592) 
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
 2026-08-14 08:59:52 +08:00
Ziang Li 9d34c2809f [FlashInfer v0.6.16] Support FlashInfer CuTe DSL NVFP4 MoE quantization (#28354) 2026-08-13 17:33:46 -07:00
ormandj c4271c3fe1 [DSpark] Fix EP1 decode performance regression (#34759) 2026-08-13 17:00:54 -07:00
weireweireandweireweire 54c44fef73 [Perf] Skip trivial DSV4 nonpaged indexer logits (#33857) 
Co-authored-by: weireweire <20922698+weireweire@users.noreply.github.com>
 2026-08-13 16:21:30 -07:00
Liangsheng Yin 151a314829 [Fix] Make the DSpark draft num_token_non_padded host-to-device copy non-blocking (#34782) 2026-08-13 16:10:54 -07:00
Khoa PhamandClaude Opus 5 81fe452810 [DCP] Share one pack kernel between both a2a backends (#34651) 
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
 2026-08-13 15:06:02 -07:00
Lianmin Zheng 8bbca87780 [Core] Organize environment variable registry (#34730) 2026-08-13 14:25:37 -07:00
jthomson04 903439044a perf(kv-events): coalesce cache events (#31479) 2026-08-13 13:36:53 -07:00
Liangsheng Yin 8554d9a5bc [Fix] Carry the backend on Kimi-K3 deferred preprocessing configs (#34766) 2026-08-13 13:30:33 -07:00
Lukas Humbel 8ad04a9bee docs(nixl): document OBJ throughput target (#30405) 2026-08-13 13:04:13 -07:00
Han YuWenhui ZhuAlex Nails
 		6b94d39f13 [Model Loading] Overlap checkpoint staging with CUDA graph capture during startup (#32017) 
Co-authored-by: Wenhui Zhu <wzhu59@asu.edu>
Co-authored-by: Alex Nails <alex.nails@radixark.ai>
 2026-08-13 12:26:25 -07:00
Shangming Cai 0772e79ee7 [CI][PD] Pin nccl rendezvous port per side to fix flaky disaggregation tests (#34755) 2026-08-14 01:44:20 +08:00
jambow0320 a82f8e1777 [PD] Add the missing Prefill bootstrap timeout for NIXL (#34692) 2026-08-14 01:08:09 +08:00
EYZLiMickXiaoyu Zhang
 		69a31ce342 fix: make Cache-DiT actually cache on MiniMax-H3 (#33827) 
Signed-off-by: YZLi <yuanli@nvidia.com>
Signed-off-by: yunch <yunch@nvidia.com>
Co-authored-by: YZLi <yuanli@nvidia.com>
Co-authored-by: Mick <mickjagger19@icloud.com>
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
 2026-08-14 00:39:58 +08:00
triple-mu ea7a6e0e99 fix(diffusion): unshard FSDP root group for custom encoder entry points (#34575) 2026-08-13 23:24:00 +08:00
Xiaoyu Zhang ebca0bbde4 [Diffusion][ERNIE] Fuse QKNorm with full-width RoPE (#34620) 2026-08-13 23:23:21 +08:00
Xiaoyu Zhang 82f7afb881 [Diffusion] Make auto residency decisions component-scoped (#34615) 2026-08-13 23:20:55 +08:00
Xiaoyu Zhang 74c0322342 [Diffusion][FLUX.2] Fuse eager AdaLN and packed SwiGLU (#34616) 2026-08-13 19:55:53 +08:00
Xiaoyu Zhang 3c1791a7df [Diffusion][HunyuanVideo] Fuse eager QKV packing and high-quality QKNorm (#34617) 2026-08-13 19:54:00 +08:00
triple-muandXiaoyu Zhang 993e24df75 [diffusion] Add --dit-layerwise-residency-policy for strided DiT residency (#34534) 
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
 2026-08-13 19:49:56 +08:00
Liu ZhenlongandXiaoyu Zhang b764194e81 [diffusion] model: support LongCat-Image (#23274) 
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
 2026-08-13 19:48:26 +08:00
Estrella-xx eea2e5d6e5 Optimize delayed sample and mrope position computation (#32637) 2026-08-13 19:15:47 +08:00
Xiaoyu ZhangandClaude Fable 5 a23670ddbf [diffusion] Wan2.2-TI2V: fuse per-token adaLN table add into contiguous slices + hoist rope cache (denoise -13.1% H100 / -12.6% H200, bit-exact; eager beats compile) (#34584) 
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
 2026-08-13 17:26:46 +08:00
Thomas WangRolaoDenthu1am9trashkk
 		34206c0017 [AMD] Run V4 MTP target-verify through the decode kernel (#34597) 
Co-authored-by: RolaoDenthu <xinyis10@illinois.edu>
Co-authored-by: 1am9trash <1am9trash>
Co-authored-by: kk <43161300+kkHuang-amd@users.noreply.github.com>
 2026-08-13 02:00:45 -07:00
Rainchar9119 dbebc1deb4 [Perf] Occupancy tuning for DSA indexer fp8-quant Q kernel (#32755) 
Signed-off-by: Rainchar9119 <1134601163@qq.com>
 2026-08-13 01:15:27 -07:00
Weiweisys-lpot-valWeiwei ZhangMa Mingfei
 		fad376d3ee [CPU][QUANT] add amx cpu support for auto-round (#29593) 
Signed-off-by: WeiweiZhang1 <weiwei1.zhang@intel.com>
Signed-off-by: sys-lpot-val <sys_lpot_val@intel.com>
Co-authored-by: sys-lpot-val <sys_lpot_val@intel.com>
Co-authored-by: Weiwei Zhang <WeiweiZhang1@users.noreply.github.com>
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
 2026-08-13 15:50:59 +08:00
Xinyi SongandThomas Wang c034120cb8 [AMD] Enable draft-extend CUDA graph and reduce bubble for MTP (#29202) 
Co-authored-by: Thomas Wang <thomawan@amd.com>
 2026-08-13 00:50:19 -07:00
AMD-yanfeiwangandZhangheng a34f81251f fix(hicache/umbp): support DeepSeek-V4 hybrid HostPoolGroup (multi-po… (#30762) 
Co-authored-by: Zhangheng <hzh0425@apache.org>
 2026-08-13 15:40:07 +08:00
jacky.cheng b7f87a2513 [AMD][Perf] Fuse GatedDeltaNet QKVZBA split/reshape/cat into a single Triton kernel for Qwen3.5-architecture MoE on HIP (#34421) 2026-08-13 00:18:35 -07:00
Ke Bao 5a5c3d309b Drop the mmlu case from the unified radix cache kit (#34667) 2026-08-13 15:16:05 +08:00
Xinguo Zhu 3f6ef01322 Optimize MiniMax-M2.7 on CPU (#31956) 2026-08-13 15:04:16 +08:00
Gabriel Wu 889c2f31aa feat(attention): add architecture-owned SM12x FA4 kernels (#32991) 2026-08-12 23:58:42 -07:00
Ke Bao ebc144ce3f Enable unified cache out-of-window slot freeing by default (#34653) 2026-08-13 14:31:42 +08:00
Mick e8c7dddfa0 [VLM] add content-addressed preprocessing cache infrastructure (#34398) 2026-08-13 14:09:07 +08:00
elvischenv 035c622a14 Reenable breakable CUDA graph for NemotronH (#34538) 2026-08-13 13:58:10 +08:00
xieminghe1undefinedxq25478xieminghe.simonXiaoyu Zhang
 		ef7208d41d [kernel] add triton moe TMA up support (#33559) 
Co-authored-by: undefined <zhouchen.arrebol@jd.com>
Co-authored-by: xq25478 <xq25478@qq.com>
Co-authored-by: xieminghe.simon <xieminghe.simon@jd.com>
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
 2026-08-13 13:29:32 +08:00
Mick 69bf601e3c fix: restore VLM nightly regression coverage (#34662) 2026-08-12 21:47:16 -07:00
Liangsheng Yin 8761b971f1 [CI] Fix nightly test failures (#34637) 2026-08-12 20:53:44 -07:00
Liangsheng Yin 26627e999d [Fix] Snapshot req.prefix_indices when the prefix cache is disabled (#34644) 2026-08-12 20:50:46 -07:00
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vstone-wClownBinhuangzhenyuclownbadmerLiangsheng YinYAMYShangming CaiMickBrayden ZhongBrayden ZhongJimmy ShongZijie XiaThomas WangsiyuYuang ChenYuang Chen黄孝君Xinyuan TongXiaoyu ZhangCursorClaude Fable 5TobyMintTobyMintCheng WanTan TrinhLifan ShenJustin TongQiaolin YuAMD-yanfeiwangQIN2DIMZhiyao JiangBrayden ZhongDevashishLal-CBDevashish LalAlex NailsMohammad Miadh AngkadBaizhou ZhangMichael GschwindweireweireweireweireKhoa PhammilesialelvischenvcctryJae B.MichaelforrestlEchOTanmay patilybyangHsiu-Chun, HungHungHaiShawBingxu ChenYC Yen-Ching TsengCherry_mingEven Zhousglang-npu-botZhiqiang XieTingwei HuangKaixigithub-actions[bot]Faradawn YangRyan StewartgjsheuJinyan YiKe BaohuangtingweiHanming LuJeremy ZhangDmitrii SergeevHao ZhangzhisbugDouglas Yanggongwei1027ilyasher-harmonicHanming Lusglang-botsglang-botJimmy Shonghnyls2002Meng, HengyuShu WangYanbin Jiangzijiec
 		bca8ed4afc [minimax m3][npu]Adaptation of Minimax M3(w8a8) for NPU platforms [1/2] (#32941) 
Signed-off-by: Devashish Lal <devcode@fb.com>
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Signed-off-by: Ryan Stewart <rystewart@nvidia.com>
Co-authored-by: ClownBin <chaobin1993@126.com>
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Co-authored-by: Shangming Cai <csmthu@gmail.com>
Co-authored-by: Mick <mickjagger19@icloud.com>
Co-authored-by: Brayden Zhong <b8zhong@uwaterloo.ca>
Co-authored-by: Brayden Zhong <brayden.zhong@radixark.ai>
Co-authored-by: Jimmy Shong <jimmysh341@gmail.com>
Co-authored-by: Zijie Xia <zijie.xia@radixark.ai>
Co-authored-by: Thomas Wang <thomawan@amd.com>
Co-authored-by: siyu <liusy58@linux.alibaba.com>
Co-authored-by: Yuang Chen <cya539102@antgroup.com>
Co-authored-by: Yuang Chen <1131578721@qq.com>
Co-authored-by: 黄孝君 <dingfangsu23@gmail.com>
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
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Co-authored-by: AMD-yanfeiwang <yanfei.wang@amd.com>
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Co-authored-by: zijiec <zijie.chen@amd.com>
 2026-08-13 11:23:14 +08:00
Xiaoyu Zhang 26579d893e [Diffusion][GLM-Image] Retune QK head LayerNorm for SM103 (#34619) 2026-08-13 10:49:13 +08:00
Liangsheng Yin 50cc1aa241 [CI] Route mmlu and GB300 MMMU-Pro evals through sgl-eval (#34477) 2026-08-12 19:33:21 -07:00