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b44e248682
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[AMD] [GLM-5.3-Flash Day 0] Enable FP8 and Quark MXFP4 MoE on gfx950 (#38546)
Co-authored-by: Raiden-Makoto <Raiden-Makoto@users.noreply.github.com>
Co-authored-by: Thomas Wang <thomawan@amd.com>
Co-authored-by: andyluo7 <andy.luo@amd.com>
Co-authored-by: Kevin Mi <mikevin920@yahoo.com>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
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2026-09-21 21:07:37 -07:00 |
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jthomson04
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15ba54bd5d
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perf(engine): avoid timed waits for Engine responses (#39486)
Signed-off-by: jthomson04 <jwillthomson19@gmail.com>
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2026-09-21 20:42:03 -07:00 |
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Cheng Wan
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1d025491f3
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[Test] Set DP size in the mocked Metal profiler test (#40667)
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2026-09-21 19:57:52 -07:00 |
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90cf471723
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[AMD] [GLM-5.3-Flash Day 0] Support non-2048 top-k widths in the DSA page-table transform (#39340)
Co-authored-by: Thomas Wang <thomawan@amd.com>
Co-authored-by: Kevin Mi <45493463+kevin-mii@users.noreply.github.com>
Co-authored-by: Kevin Mi <mikevin920@yahoo.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
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2026-09-21 19:50:17 -07:00 |
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jacky.cheng
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bc30fa1759
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[AMD][Fix] AgentX HIP TPOT regression when SGLANG_SIMULATE_ACC_LEN is set (#40598)
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2026-09-21 19:16:15 -07:00 |
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Cheng Wan
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9eda772a21
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[Test] Handle tied top-k indices in graph-pool logprob regression (#40661)
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2026-09-21 19:02:43 -07:00 |
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Mohammad Miadh Angkadandmmangkad
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e332e1b84e
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[Fix] Don't write conv state from the fused KDA verify kernel (#39524)
Co-authored-by: mmangkad <mohammad.angkad@radixark.ai>
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2026-09-21 18:33:03 -07:00 |
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Dayananda VandClaude Opus 5
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35eb7cf8d6
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[Intel][XPU][KVCanary] Enable KV Canary on Intel XPU (#33520)
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
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2026-09-22 09:19:01 +08:00 |
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Ma Mingfei
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046cd6f4ea
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[XPU][ci]: disable XPU NIXL disaggregation test (#40540)
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2026-09-22 09:02:22 +08:00 |
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Khoa Pham
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c4d3770a68
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[Kimi K3] Fix CUDA graph stream explosion (#40640)
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2026-09-21 17:49:50 -07:00 |
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Cheng Wan
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98c8dee23b
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Fix lint failure from draft-decode window test location (#40654)
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2026-09-21 17:41:00 -07:00 |
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042b6a488f
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[AMD] [GLM-5.3-Flash Day 0] Enable zero-RoPE MHA prefill on ROCm (#39338)
Co-authored-by: Thomas Wang <thomawan@amd.com>
Co-authored-by: Kevin Mi <45493463+kevin-mii@users.noreply.github.com>
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2026-09-21 17:38:07 -07:00 |
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avalliappan-nvidia
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61d0cf2074
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[Spec] Windowed draft-decode attention for built-in EAGLE / MTP drafts (#32673)
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2026-09-22 08:17:57 +08:00 |
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Vedant V JhaveriandCopilot
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9fdb71732a
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Avoid materializing GDN QKV tensors during target verification (#33778)
Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
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2026-09-21 17:04:18 -07:00 |
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Cheng Wan
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506698761d
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[unified-memory] Hierarchical cache for every unified pool shape (#37507)
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2026-09-21 16:50:37 -07:00 |
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Cheng Wan
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22587fb15c
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[Fix] Run KV canary hooks for context-parallel prefill (#40642)
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2026-09-21 16:46:22 -07:00 |
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Yuxuan ZhangandXinyuan Tong
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00986c81be
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Support GLM-5.3-Flash hybrid attention CPU offload and PD index mapping (#40310)
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
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2026-09-21 16:03:03 -07:00 |
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YAMY
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0229025127
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[Spec][PP] Launch extend microbatches before the spec output exchange (#40499)
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2026-09-21 15:47:03 -07:00 |
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Liangsheng Yin
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a5c2cc517c
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[CI] Split the CI control labels into four axes and resolve them live (#40527)
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2026-09-21 15:37:28 -07:00 |
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8bde82c0ad
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[AMD] [GLM-5.3-Flash Day 0] Build the fused DSA k-pool top-k JIT kernel on HIP (#39339)
Co-authored-by: Raiden-Makoto <Raiden-Makoto@users.noreply.github.com>
Co-authored-by: Thomas Wang <thomawan@amd.com>
Co-authored-by: Kevin Mi <mikevin920@yahoo.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
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2026-09-21 15:24:44 -07:00 |
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Cheng Wan
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acac4dd9d9
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[Refactor] Clean up parallel runtime comments (#40632)
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2026-09-21 14:32:22 -07:00 |
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jacky.cheng
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e0c2e8dc4d
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[AMD] Tune Qwen3.5 TP4 GDN recurrent launch on gfx950 (#39987)
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2026-09-21 13:20:54 -07:00 |
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Liangsheng Yin
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1ed6822039
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[Test] Anchor basic_perf thresholds to each metric's measured spread (#40617)
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2026-09-21 13:02:10 -07:00 |
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11e661fd45
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[Fix] Don't free the multi-CTAs KV counter the decode graphs captured (#39175)
Co-authored-by: mmangkad <mohammad.angkad@radixark.ai>
Co-authored-by: kpham-sgl <khoa.pham@radixark.ai>
Co-authored-by: Claude Fable 5.1 <noreply@anthropic.com>
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2026-09-21 12:58:48 -07:00 |
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Cheng Wan
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44bdf225d8
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Fix lint failure from MXFP8 reserved-slot test location (#40618)
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2026-09-21 12:31:11 -07:00 |
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Cheng Wan
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bccf691b22
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Bringing the parallel runtime up becomes a phase, not a side effect (#40345)
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2026-09-21 12:29:50 -07:00 |
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Cheng Wan
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1d3243d05f
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Take the parallel getters off the package's public surface (#40344)
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2026-09-21 12:27:50 -07:00 |
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Cheng Wan
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970e946e4f
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Retire the per-runner parallel record (#40343)
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2026-09-21 12:26:40 -07:00 |
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Cheng Wan
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73f071db52
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Deprecate the parallel getters the context answers, and ratchet them shut (#40342)
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2026-09-21 12:25:32 -07:00 |
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Cheng Wan
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65be3fa71a
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A runner and the objects it builds freeze the placement they describe (#40341)
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2026-09-21 12:24:17 -07:00 |
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Cheng Wan
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2d0e94e3a3
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Check the topology identities where the layout is written, and build at the published widths (#40340)
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2026-09-21 12:22:59 -07:00 |
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Cheng Wan
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0db1a93adb
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State the draft's whole topology in its scope, and read the rest from the context (#40339)
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2026-09-21 12:19:38 -07:00 |
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ae7a516ba7
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feat: use XGrammar V4.1 DSML parameter constraints (#39026)
Co-authored-by: yuchuan <yuchuan.7streams@gmail.com>
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
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2026-09-21 12:12:28 -07:00 |
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jacky.cheng
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90b3f8544c
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[AMD] Use Triton softmax routing for Qwen3.5 on gfx950 (#39986)
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2026-09-21 12:02:29 -07:00 |
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cctry
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7a6191c4b9
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Preallocate HiCache MHA staging before post-capture KV sizing (#40256)
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2026-09-21 10:44:29 -07:00 |
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cctry
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7ad55e4386
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[HiCache] TMA-staged host<->device KV transfer kernel (sm_90+) (#40278)
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2026-09-21 10:38:23 -07:00 |
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Eric.Chin.AMDandThomas Wang
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3c71bb018a
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[AMD] Enable GLM DSA prefill top-k to the v2 kernel (#37889)
Co-authored-by: Thomas Wang <thomawan@amd.com>
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2026-09-21 10:31:07 -07:00 |
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5a6a1bb883
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[mxfp8-kv] Skip writes to the reserved CUDA-graph padding slot (#35351)
Co-authored-by: Claude Opus 4.8 <noreply@anthropic.com>
Co-authored-by: Ke Bao <ispobaoke@gmail.com>
Co-authored-by: Sam Shleifer <sam@thinkingmachines.ai>
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2026-09-22 01:21:25 +08:00 |
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Liangsheng Yin
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800613a74b
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[Test] Split the serving perf tests by topic into basic_perf/ and route their thresholds through a kit (#40505)
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2026-09-21 10:05:57 -07:00 |
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Sage
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14e9c40a72
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[Observability] Expose python/rust frontend identity in /server_info (#39993)
Signed-off-by: Sage Ahrac <sagiahrak@gmail.com>
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2026-09-21 23:32:52 +08:00 |
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b63f8416b3
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[Feature] Gigachat 3.5 support (#29189)
Co-authored-by: Stanislav Petrov <stapetrov@sberbank.ru>
Co-authored-by: Viacheslav Barinov <vvadbarinov@sberbank.ru>
Co-authored-by: Viacheslav <viacheslav.teh@gmail.com>
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
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2026-09-21 14:37:55 +08:00 |
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kpjeeja
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b54d5b7c7b
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disaggregation: Fix FakeKVSender queue accumulation (#28652)
Signed-off-by: KP, Jeeja <jeeja.kp@intel.com>
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2026-09-21 14:27:05 +08:00 |
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skyler-apdx
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f5f3c38aad
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[Fix] Preserve YaRN scaling when extending rotary caches (#38786)
|
2026-09-21 14:14:05 +08:00 |
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AMRUTHA MandMa Mingfei
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d20cd9d77f
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[XPU]Enable HiSparse hierarchical sparse KV cache on Intel XPU (#32792)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
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2026-09-21 14:07:49 +08:00 |
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jianzhao-xu
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62ba964848
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Fix: post-load staging regression breaks offload meta/sharded_gpu modes (#38779)
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2026-09-21 11:19:07 +08:00 |
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Xueshen Liu
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ab03a8e7eb
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[Perf] Fork-safe import: no CUDA context at import time, lighter argument parsing (#40201)
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2026-09-21 10:48:35 +08:00 |
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zhaozx-cn
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176dbcb85d
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[npu]add chunk gdn kernel and unify ssm state layout for ascend gdn backend (#36187)
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2026-09-21 09:51:19 +08:00 |
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Liangsheng Yin
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76a9065bef
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[Fix] Raise on undelivered embeddings in send_with_url, fix broken tests (#40502)
|
2026-09-20 17:35:27 -07:00 |
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Liangsheng Yin
|
acd20a516e
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[CI] Give the kernel lane a 5090 suite and move kernel-only tests off the general lane (#40496)
|
2026-09-20 16:46:53 -07:00 |
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|
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42875bcd2a
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fix(modelopt): dispatch NVFP4 MoE on the cached backend, not the live global (#38932)
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Co-authored-by: Po-Han Huang (NVIDIA) <53919306+nvpohanh@users.noreply.github.com>
|
2026-09-20 19:28:54 -04:00 |
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