Mohammad Miadh Angkad
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c5367fa964
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[CI] Fix stale ServerArgs fake in chunked-SGMV LoRA test (#38315)
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2026-09-07 04:25:12 -07:00 |
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Cheng Wan
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b5766336d4
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[Perf] Unified memory: close the DCP decode gap on Blackwell (#37926)
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2026-09-07 01:10:44 -07:00 |
|
 Xiaoyu ZhangandMick Qian
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4d23a4fa6d
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[Test] Consolidate test cleanup and CI taxonomy (net -11.4K lines) (#37436)
Co-authored-by: Mick Qian <mickqian@users.noreply.github.com>
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2026-09-07 15:13:59 +08:00 |
|
   
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a8b2f36dee
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[kernel] add fused silu mul quant fp8 (#37376)
Co-authored-by: undefined <zhouchen.arrebol@jd.com>
Co-authored-by: xq25478 <xq25478@qq.com>
Co-authored-by: xieminghe.simon <xieminghe.simon@jd.com>
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
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2026-09-07 11:39:11 +08:00 |
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 sglang-botandsglang-bot
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6252993afe
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chore: update CI test est_time values (#38238)
Co-authored-by: sglang-bot <sglang-bot@users.noreply.github.com>
|
2026-09-06 17:49:41 -07:00 |
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+2        
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97c6978369
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GLM-5.3-Flash support (#36507)
Co-authored-by: zRzRzRzRzRzRzR <Yuxuan.Zhang2@liverpool.ac.uk>
Co-authored-by: Shijin Zhang <75300765+Dovis01@users.noreply.github.com>
Co-authored-by: zanes-ops <zanes@nvidia.com>
Co-authored-by: Baizhou Zhang <sobereddiezhang@gmail.com>
Co-authored-by: Jian Chen <jianchen0311@gmail.com>
Co-authored-by: zijiexia <37504505+zijiexia@users.noreply.github.com>
Co-authored-by: andyluo7 <43718156+andyluo7@users.noreply.github.com>
Co-authored-by: Ehsan Akhgari <ehsan.akhgari@gmail.com>
Co-authored-by: kpham-sgl <khoa.pham@radixark.ai>
Co-authored-by: BBuf <1182563586@qq.com>
Co-authored-by: Raiden Makoto <81530826+Raiden-Makoto@users.noreply.github.com>
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2026-09-06 02:27:59 -07:00 |
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Liangsheng Yin
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f5819b09bf
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Revert "[AMD][DSV4] Fix unified-KV pool sizing and SWA ring accounting" (#38163)
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2026-09-05 17:28:46 -07:00 |
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yuttian1
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514b45fd34
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[AMD][DSV4] Fix unified-KV pool sizing and SWA ring accounting (#30315)
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2026-09-05 16:39:40 -07:00 |
|
 Xiaoyu ZhangandWaterpine
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ccf9fe6590
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[Kernel] Add KDA FP8 skinny GEMM for SM120 (#38082)
Co-authored-by: Waterpine <biansonghz@gmail.com>
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2026-09-05 22:27:06 +08:00 |
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Xiaoyu Zhang
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dc2843801d
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perf(lfm2): fuse gating and short convolution on SM90 (#37622)
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2026-09-05 21:52:16 +08:00 |
|
 
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bd16c22a04
|
[diffusion] fuse LingBot MoE group-limited top-k index selection (#38044)
Co-authored-by: BBuf <bbuf@users.noreply.github.com>
Co-authored-by: Mick Qian <mickqian@users.noreply.github.com>
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2026-09-05 18:12:30 +08:00 |
|
 DayuxiaoshuiandXiaoyu Zhang
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50c1bf0db0
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[Diffusion] Port the Wan VAE decoder fast paths to the Qwen-Image VAE (#38020)
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
|
2026-09-05 18:02:33 +08:00 |
|
 Xiaoyu ZhangandBBuf
|
d49180019b
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fix(moe): cast filtered-activation expert_ids to int32 for torch.compile (#38085)
Co-authored-by: BBuf <bbuf@users.noreply.github.com>
|
2026-09-05 17:13:07 +08:00 |
|
 
|
55bf3380e0
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Support Hy4-preview (#36805)
Co-authored-by: BBuf <1182563586@qq.com>
Co-authored-by: alphabetc1 <2508695655@qq.com>
|
2026-09-04 18:03:49 -07:00 |
|
Xiaoyu Zhang
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54c2c99feb
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[Diffusion] Fuse LingBot per-token gated residual and RMSNorm modulate (#37910)
|
2026-09-04 14:35:13 +08:00 |
|
 
|
2bb25dc18b
|
[Speculative Decoding] Add native UNO serving support (#37667)
Co-authored-by: drproduck <drproduck@MacBook-Air-2.local>
Co-authored-by: BBuf <1182563586@qq.com>
|
2026-09-03 20:08:41 +08:00 |
|
 Xinyi SongandThomas Wang
|
7ed29eba80
|
[AMD] Fix FP4 indexer OOR (#37660)
Co-authored-by: Thomas Wang <1am9trash@gmail.com>
|
2026-09-03 01:49:46 -07:00 |
|
 
|
3bac084d4e
|
[Model] Add native IFM K2 Horizon serving support (#37654)
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
|
2026-09-03 16:39:43 +08:00 |
|
 YC Yen-Ching TsengandPhil Li
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1fb85053e7
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[AMD][Diffusion] Migrate FlyDSL fused norm kernels to the v0.3.0 stable API (#36349)
Co-authored-by: Phil Li <haicli@amd.com>
|
2026-09-02 23:03:08 -07:00 |
|
 Alex NailsandAlison Shao
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28262c20df
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[CI][RFC] Replace black-jupyter with ruff-format (#37210)
Co-authored-by: Alison Shao <a.shao@wustl.edu>
|
2026-09-02 19:46:08 -07:00 |
|
  
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f8cbf000f4
|
[AMD] Enable FP4 indexer for Deepseek V4 (#37353)
Co-authored-by: 1am9trash <1am9trash@gmail.com>
Co-authored-by: AMD-yanfeiwang <256076023+AMD-yanfeiwang@users.noreply.github.com>
Co-authored-by: Thomas Wang <thomawan@amd.com>
|
2026-09-02 09:45:08 -07:00 |
|
 Khoa PhamandClaude Opus 5
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c66a285c94
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[Kernel] GLM 5.3 Flash related kernels (ported from #36507) (#37477)
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
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2026-09-01 22:17:09 -07:00 |
|
 kkandwunhuang
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dc276264cb
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[AMD] Perf Kimi-K3 fuse ROCm KDA decode boundary (#34198)
Co-authored-by: wunhuang <wunhuang@amd.com>
|
2026-09-01 18:35:48 -07:00 |
|
 Xiaoyu ZhangandCursor
|
f4c17fed07
|
[Diffusion] Fuse FLUX.2 NVFP4 FC1, SwiGLU, and FC2 quantization (#37096)
Co-authored-by: Cursor <cursoragent@cursor.com>
|
2026-09-02 08:21:14 +08:00 |
|
 
|
c593527f33
|
[Kernel] Add KDA NVFP4 GEMM for Qwen3.x on SM120 (#36865)
Co-authored-by: Song Bian <biansonghz@gmail.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
|
2026-09-02 08:16:54 +08:00 |
|
 
|
33428d3dae
|
Fix GPU kernel ordering and MXFP8 quantization dispatch (#37331)
Co-authored-by: Pranjal Shankhdhar <pranjalssh@meta.com>
Co-authored-by: Chengze Fan <fancz2002@gmail.com>
|
2026-09-01 17:09:44 -07:00 |
|
YAMY
|
221a6273ce
|
[Kernel] Avoid zero-bias allocation in fused softmax routing (#36811)
|
2026-09-01 16:29:57 -07:00 |
|
 DarkSharpnessandClaude Opus 5
|
cb6dd58fbe
|
[Kernel] Replace dsv3_router_gemm with the unified tiny GEMM (#34693)
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
|
2026-09-01 23:00:21 +08:00 |
|
Xiaoyu Zhang
|
5993f91f84
|
[Kernel] Register merged diffusion agent kernels with KDA backend (#37385)
|
2026-09-01 22:51:10 +08:00 |
|
 DarkSharpnessandClaude Opus 5
|
b6c06e1efb
|
[DSA] Drop the redundant 512 from the top-k transform entry-point names (#36831)
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
|
2026-09-01 22:37:03 +08:00 |
|
Even Zhou
|
00689c0c94
|
[CI] Add entrypoint to hc_combine test for standalone execution (#37406)
|
2026-09-01 22:08:00 +08:00 |
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eeecho
|
b68702be99
|
[DSV4] hc-prenorm: fuse the combine step into a Triton kernel (#35118)
|
2026-09-01 02:04:05 -07:00 |
|
Ziang Li
|
5edcd0a445
|
[FlashInfer V0.6.18] feat(dsv4): support --dsa-topk-backend flashinfer with fused top-k (#33237)
|
2026-09-01 01:18:10 -07:00 |
|
 Xiaoyu ZhangandCursor
|
1c3ad92438
|
[Diffusion] Fuse FLUX.2 ModelOpt FP8 producers and QKV packing (#37162)
Co-authored-by: Cursor <cursoragent@cursor.com>
|
2026-09-01 16:14:29 +08:00 |
|
 
|
71cee04ebe
|
[Diffusion] Optimize Qwen-Image TP collectives and attention (#36680)
Co-authored-by: Mick <mickjagger19@icloud.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
|
2026-09-01 10:28:37 +08:00 |
|
 Xiaoyu ZhangandCursor
|
175973d834
|
[Diffusion] Fuse Qwen-Image residual norm and NVFP4 quantization (#37129)
Co-authored-by: Cursor <cursoragent@cursor.com>
|
2026-09-01 08:54:10 +08:00 |
|
 Xiaoyu ZhangandCursor
|
6715debb2a
|
[Diffusion] Fuse Qwen-Image FP8 QKV projection and Blackwell epilogue (#37123)
Co-authored-by: Cursor <cursoragent@cursor.com>
|
2026-09-01 08:34:41 +08:00 |
|
 Liangsheng YinandBaizhou Zhang
|
95f0f41021
|
[CI] Move tests onto the right CI stages (#34074)
Co-authored-by: Baizhou Zhang <sobereddiezhang@gmail.com>
|
2026-08-31 12:39:59 -07:00 |
|
Xiaoyu Zhang
|
52e1c24744
|
[Diffusion] Fuse FLUX.2 token concatenation and NVFP4 quantization (#37141)
|
2026-08-31 21:33:02 +08:00 |
|
Xiaoyu Zhang
|
771e613d96
|
[Diffusion] Fuse Qwen-Image final adaptive LayerNorm (#37144)
|
2026-08-31 18:22:20 +08:00 |
|
 Xiaoyu ZhangandCursor
|
1ed9bfac2c
|
[Diffusion] Fuse Qwen-Image FP8 norm and activation quantization (#37156)
Co-authored-by: Cursor <cursoragent@cursor.com>
|
2026-08-31 18:19:42 +08:00 |
|
Xiaoyu Zhang
|
bb5e619860
|
[diffusion] perf: absorb Qwen-Image output projection biases (#37116)
|
2026-08-31 08:25:37 +08:00 |
|
Xiaoyu Zhang
|
5ab97c4f44
|
[Diffusion] Cache Qwen-Image modulation across serial CFG branches (#37090)
|
2026-08-31 01:40:29 +08:00 |
|
Xiaoyu Zhang
|
8c28cdd116
|
[Diffusion][Kernel] Fuse Wan2.2 NVFP4 bias + GELU on Blackwell (#37075)
|
2026-08-31 01:37:35 +08:00 |
|
Jason Wiemels
|
e635577431
|
[rotary] Fix the fused Qwen3.5 RoPE kernel discarding mrope height and width (#34446)
|
2026-08-30 15:37:40 +08:00 |
|
Alex Nails
|
78fa921189
|
[ROCm] Fix QuickReduce fp16 saturation corrupting bf16 all-reduces (106M non-finite -> 0, +0.3%) (#34484)
|
2026-08-29 22:08:17 -07:00 |
|
 Alex NailsandClaude Opus 5
|
00fbb6e8ac
|
[Perf] Tune the W4AFP8 DeepEP low-latency requant launch geometry (#35760)
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
|
2026-08-29 16:03:01 -07:00 |
|
 
|
3760296be8
|
[PD] Pack DCP1→DCP-N PD KV transfers into dest-contiguous RDMA blocks (#35762)
Co-authored-by: Cursor <cursoragent@cursor.com>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
|
2026-08-28 21:41:30 -07:00 |
|
+8        
|
5f216fc33f
|
qwen 3.8 rebase (#35758)
Co-authored-by: cherichy <cherichy@outlook.com>
Co-authored-by: guangyunh-nv <guangyunh@nvidia.com>
Co-authored-by: jiahanc <jiahanc@nvidia.com>
Co-authored-by: jinyangyuan-nvidia <joyuan@nvidia.com>
Co-authored-by: Cheng Hang <chang@nvidia.com>
Co-authored-by: Yicheng Qiang <yqiang@nvidia.com>
Co-authored-by: Sam Li <lsam@nvidia.com>
Co-authored-by: Tom-Zheng <tizheng@nvidia.com>
Co-authored-by: Yangmin Li <yangminl@nvidia.com>
Co-authored-by: xiaoweiw-nv <xiaoweiw@nvidia.com>
Co-authored-by: Zheng Li <lizheng.cs@zju.edu.cn>
Co-authored-by: yizhang2077 <1109276519@qq.com>
Co-authored-by: Ke Bao <ispobaoke@gmail.com>
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
Co-authored-by: Yuhao Yang <47235274+yhyang201@users.noreply.github.com>
Co-authored-by: Zijie Xia <zijie.xia@radixark.ai>
Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
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2026-08-28 20:41:34 -07:00 |
|
 valechenandHAI
|
4944e50e2c
|
[AMD] Add Work-Centric (Lean) Attention: a persistent-CTA decode kernel for long-context serving (#33576)
Signed-off-by: Valerie Chen <valechen@amd.com>
Co-authored-by: HAI <hixiao@gmail.com>
|
2026-08-28 17:00:44 -07:00 |
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