 Liangsheng YinandBaizhou Zhang
|
95f0f41021
|
[CI] Move tests onto the right CI stages (#34074)
Co-authored-by: Baizhou Zhang <sobereddiezhang@gmail.com>
|
2026-08-31 12:39:59 -07:00 |
|
|
|
514b997e6c
|
Register CPU CI for 17 e2e tests and partition xeon base-c suite (#35227)
Co-authored-by: Zhang, Mingxu <mingxu.zhang@intel.com>
Co-authored-by: MingxuZh <109504044+MingxuZh@users.noreply.github.com>
Co-authored-by: Copilot Autofix powered by AI <175728472+Copilot@users.noreply.github.com>
Co-authored-by: Claude <noreply@anthropic.com>
|
2026-08-24 10:49:38 +08:00 |
|
|
jundu
|
e04ed05193
|
[CI] reduce CPU CI scope with base-c suite (#28623)
|
2026-06-24 16:18:06 +08:00 |
|
|
MingxuZh
|
21ba329dac
|
[Xeon] CPU CI enhancement for Intel Xeon platforms (#24649)
|
2026-05-28 10:49:04 +08:00 |
|
|
Liangsheng Yin
|
b7d62bd724
|
[CI] Rename basic CI stage-a/b/c -> base-a/b/c for symmetry with extra CI (#25420)
|
2026-05-15 18:26:55 -07:00 |
|
|
Lianmin Zheng
|
814202704b
|
ci: unify PR test suite naming (#21187)
|
2026-03-23 00:18:45 -07:00 |
|
|
Lianmin Zheng
|
cea79530f8
|
ci: merge CPU default and stage-a-cpu-only suites (#20992)
|
2026-03-20 00:04:55 -07:00 |
|
|
fzyzcjy
|
d7aa0ce72f
|
Support multiple engines for router simulation in schedule simulator (#16368)
|
2026-01-04 11:46:05 +08:00 |
|
|
fzyzcjy
|
24e116ef6a
|
Enhance schedule simulator and add several e2e scenarios (#16357)
|
2026-01-04 10:02:38 +08:00 |
|
|
fzyzcjy
|
8ca9597057
|
Tiny support sticky routing algorithm in schedule simulator (#16355)
|
2026-01-04 08:36:52 +08:00 |
|
|
fzyzcjy
|
ef5ac6f01e
|
Support shared prefix (gsp) in schedule simulator (#16353)
|
2026-01-04 08:03:16 +08:00 |
|
|
fzyzcjy
|
e139d2aa76
|
Super tiny fix CI (#16351)
|
2026-01-04 07:24:46 +08:00 |
|
|
fzyzcjy
|
87ef05e2e1
|
Support simple schedule simulator (#16344)
|
2026-01-03 22:05:40 +08:00 |
|