 Liangsheng Yin
|
a5c2cc517c
|
[CI] Split the CI control labels into four axes and resolve them live (#40527)
|
2026-09-21 15:37:28 -07:00 |
|
|
|
8bde82c0ad
|
[AMD] [GLM-5.3-Flash Day 0] Build the fused DSA k-pool top-k JIT kernel on HIP (#39339)
Co-authored-by: Raiden-Makoto <Raiden-Makoto@users.noreply.github.com>
Co-authored-by: Thomas Wang <thomawan@amd.com>
Co-authored-by: Kevin Mi <mikevin920@yahoo.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
|
2026-09-21 15:24:44 -07:00 |
|
|
Cheng Wan
|
acac4dd9d9
|
[Refactor] Clean up parallel runtime comments (#40632)
|
2026-09-21 14:32:22 -07:00 |
|
|
jacky.cheng
|
e0c2e8dc4d
|
[AMD] Tune Qwen3.5 TP4 GDN recurrent launch on gfx950 (#39987)
|
2026-09-21 13:20:54 -07:00 |
|
|
Liangsheng Yin
|
1ed6822039
|
[Test] Anchor basic_perf thresholds to each metric's measured spread (#40617)
|
2026-09-21 13:02:10 -07:00 |
|
|
|
11e661fd45
|
[Fix] Don't free the multi-CTAs KV counter the decode graphs captured (#39175)
Co-authored-by: mmangkad <mohammad.angkad@radixark.ai>
Co-authored-by: kpham-sgl <khoa.pham@radixark.ai>
Co-authored-by: Claude Fable 5.1 <noreply@anthropic.com>
|
2026-09-21 12:58:48 -07:00 |
|
|
Cheng Wan
|
44bdf225d8
|
Fix lint failure from MXFP8 reserved-slot test location (#40618)
|
2026-09-21 12:31:11 -07:00 |
|
|
Cheng Wan
|
bccf691b22
|
Bringing the parallel runtime up becomes a phase, not a side effect (#40345)
|
2026-09-21 12:29:50 -07:00 |
|
|
Cheng Wan
|
1d3243d05f
|
Take the parallel getters off the package's public surface (#40344)
|
2026-09-21 12:27:50 -07:00 |
|
|
Cheng Wan
|
970e946e4f
|
Retire the per-runner parallel record (#40343)
|
2026-09-21 12:26:40 -07:00 |
|
|
Cheng Wan
|
73f071db52
|
Deprecate the parallel getters the context answers, and ratchet them shut (#40342)
|
2026-09-21 12:25:32 -07:00 |
|
|
Cheng Wan
|
65be3fa71a
|
A runner and the objects it builds freeze the placement they describe (#40341)
|
2026-09-21 12:24:17 -07:00 |
|
|
Cheng Wan
|
2d0e94e3a3
|
Check the topology identities where the layout is written, and build at the published widths (#40340)
|
2026-09-21 12:22:59 -07:00 |
|
|
Cheng Wan
|
0db1a93adb
|
State the draft's whole topology in its scope, and read the rest from the context (#40339)
|
2026-09-21 12:19:38 -07:00 |
|
|
|
ae7a516ba7
|
feat: use XGrammar V4.1 DSML parameter constraints (#39026)
Co-authored-by: yuchuan <yuchuan.7streams@gmail.com>
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
|
2026-09-21 12:12:28 -07:00 |
|
|
jacky.cheng
|
90b3f8544c
|
[AMD] Use Triton softmax routing for Qwen3.5 on gfx950 (#39986)
|
2026-09-21 12:02:29 -07:00 |
|
|
cctry
|
7a6191c4b9
|
Preallocate HiCache MHA staging before post-capture KV sizing (#40256)
|
2026-09-21 10:44:29 -07:00 |
|
|
cctry
|
7ad55e4386
|
[HiCache] TMA-staged host<->device KV transfer kernel (sm_90+) (#40278)
|
2026-09-21 10:38:23 -07:00 |
|
|
Eric.Chin.AMDandThomas Wang
|
3c71bb018a
|
[AMD] Enable GLM DSA prefill top-k to the v2 kernel (#37889)
Co-authored-by: Thomas Wang <thomawan@amd.com>
|
2026-09-21 10:31:07 -07:00 |
|
|
|
5a6a1bb883
|
[mxfp8-kv] Skip writes to the reserved CUDA-graph padding slot (#35351)
Co-authored-by: Claude Opus 4.8 <noreply@anthropic.com>
Co-authored-by: Ke Bao <ispobaoke@gmail.com>
Co-authored-by: Sam Shleifer <sam@thinkingmachines.ai>
|
2026-09-22 01:21:25 +08:00 |
|
|
Liangsheng Yin
|
800613a74b
|
[Test] Split the serving perf tests by topic into basic_perf/ and route their thresholds through a kit (#40505)
|
2026-09-21 10:05:57 -07:00 |
|
|
Sage
|
14e9c40a72
|
[Observability] Expose python/rust frontend identity in /server_info (#39993)
Signed-off-by: Sage Ahrac <sagiahrak@gmail.com>
|
2026-09-21 23:32:52 +08:00 |
|
|
|
b63f8416b3
|
[Feature] Gigachat 3.5 support (#29189)
Co-authored-by: Stanislav Petrov <stapetrov@sberbank.ru>
Co-authored-by: Viacheslav Barinov <vvadbarinov@sberbank.ru>
Co-authored-by: Viacheslav <viacheslav.teh@gmail.com>
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
|
2026-09-21 14:37:55 +08:00 |
|
|
kpjeeja
|
b54d5b7c7b
|
disaggregation: Fix FakeKVSender queue accumulation (#28652)
Signed-off-by: KP, Jeeja <jeeja.kp@intel.com>
|
2026-09-21 14:27:05 +08:00 |
|
|
skyler-apdx
|
f5f3c38aad
|
[Fix] Preserve YaRN scaling when extending rotary caches (#38786)
|
2026-09-21 14:14:05 +08:00 |
|
|
AMRUTHA MandMa Mingfei
|
d20cd9d77f
|
[XPU]Enable HiSparse hierarchical sparse KV cache on Intel XPU (#32792)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
|
2026-09-21 14:07:49 +08:00 |
|
|
jianzhao-xu
|
62ba964848
|
Fix: post-load staging regression breaks offload meta/sharded_gpu modes (#38779)
|
2026-09-21 11:19:07 +08:00 |
|
|
Xueshen Liu
|
ab03a8e7eb
|
[Perf] Fork-safe import: no CUDA context at import time, lighter argument parsing (#40201)
|
2026-09-21 10:48:35 +08:00 |
|
|
zhaozx-cn
|
176dbcb85d
|
[npu]add chunk gdn kernel and unify ssm state layout for ascend gdn backend (#36187)
|
2026-09-21 09:51:19 +08:00 |
|
|
Liangsheng Yin
|
76a9065bef
|
[Fix] Raise on undelivered embeddings in send_with_url, fix broken tests (#40502)
|
2026-09-20 17:35:27 -07:00 |
|
|
Liangsheng Yin
|
acd20a516e
|
[CI] Give the kernel lane a 5090 suite and move kernel-only tests off the general lane (#40496)
|
2026-09-20 16:46:53 -07:00 |
|
|
|
42875bcd2a
|
fix(modelopt): dispatch NVFP4 MoE on the cached backend, not the live global (#38932)
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Co-authored-by: Po-Han Huang (NVIDIA) <53919306+nvpohanh@users.noreply.github.com>
|
2026-09-20 19:28:54 -04:00 |
|
|
Mohammad Miadh Angkadandmmangkad
|
2fa6b94e34
|
[Perf] Fuse the glm5_next mHC attn->MLP boundary (#39200)
Co-authored-by: mmangkad <mohammad.angkad@radixark.ai>
|
2026-09-20 16:20:37 -07:00 |
|
|
|
f31a7bd45c
|
Use pinned memory for asynchronous sampling metadata transfers (#39777)
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
Co-authored-by: hnyls2002 <lsyincs@gmail.com>
|
2026-09-20 15:31:31 -07:00 |
|
|
Harmya Bhatt
|
95521da18d
|
[DeepSeek-V4.1] Bound dense prefill indexer memory (#40217)
|
2026-09-20 14:43:19 -07:00 |
|
|
Liangsheng Yin
|
f6483e479f
|
[Test] Drop cause-less disabled tests, fix XPU lane, demote quality gates off base-c (#40288)
|
2026-09-20 14:36:02 -07:00 |
|
|
|
d229952e25
|
[Fix] Preserve model runner contracts in prefill CUDA graphs (#35452)
Co-authored-by: Oasis-Git <ayw.sirius19@gmail.com>
Co-authored-by: Ke Bao <ispobaoke@gmail.com>
|
2026-09-20 13:53:14 -07:00 |
|
|
Khoa Pham
|
b3e4d198af
|
[PD] Bound cached-prefix DCP transfers by pack capacity (#40376)
|
2026-09-21 01:17:15 +08:00 |
|
|
Jimmy ShongandYangmin Li
|
e97614d10c
|
[Qwen4-Exp] Build the offloaded PLE table on the meta device so --ple-offload-embedding never materialises it on the accelerator (#39928)
Co-authored-by: Yangmin Li <yangminl@nvidia.com>
|
2026-09-20 08:28:25 -07:00 |
|
|
ZY Y
|
5f017ffabb
|
Update test cases and performance testing framework (#40392)
|
2026-09-20 22:42:00 +08:00 |
|
|
Mohammad Miadh AngkadandMohammad Angkad
|
8923f4d779
|
[Test] Fix optimistic prefill disaggregation test after mamba radix cache removal (#40469)
Co-authored-by: Mohammad Angkad <mohammad.angkad@radixark.ai>
|
2026-09-20 22:39:34 +08:00 |
|
|
Liangsheng Yin
|
0024efa0de
|
[CI] Derive registered-test kind from the registry call instead of the path (#40294)
|
2026-09-20 02:01:22 -07:00 |
|
|
HuangJi
|
2a0cb2f04e
|
[Diffusion][MiniMax-H3] Add SM120 Sage compute for SubBlock sparse attention (#40116)
|
2026-09-20 16:40:28 +08:00 |
|
|
Liangsheng Yin
|
dc002c85fc
|
[Test] Fix OOT DFlash hook test resolving the draft config over the network (#40427)
|
2026-09-20 01:25:34 -07:00 |
|
|
Shuwen WangandSeokhoon Kang
|
9f3d275940
|
[HiCache] Fix sparse hybrid transfer layer IDs (#37870)
Co-authored-by: Seokhoon Kang <sh.kang@postech.ac.kr>
|
2026-09-20 16:24:24 +08:00 |
|
|
amd-danli103andHAI
|
e54009240a
|
[AMD][DSV4] feat: enable DSpark with fp8 unified_kv on gfx950 (#38901)
Co-authored-by: HAI <hixiao@gmail.com>
|
2026-09-20 01:16:39 -07:00 |
|
|
Ke Bao
|
a8a4d86be9
|
Remove swa and mamba radix cache (#40313)
|
2026-09-20 16:16:27 +08:00 |
|
|
Qiaolin Yu
|
f4c256354c
|
[kimi k3][pd disagg] support pp prefill + dcp decode with dspark (#40045)
|
2026-09-20 00:15:28 -07:00 |
|
|
Mohammad Miadh AngkadandMohammad Angkad
|
22f02cc339
|
[Test] Fix scheduler fixtures after prefill burst counting (#40411)
Co-authored-by: Mohammad Angkad <mohammad.angkad@radixark.ai>
|
2026-09-20 00:08:04 -07:00 |
|
|
|
99a44c88d4
|
Add out-of-tree DFlash extension points (#38740)
Co-authored-by: Yuhan Chen <yuhanc@fb.com>
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
|
2026-09-20 14:54:46 +08:00 |
|