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12957 Commits
Author SHA1 Message Date
Michele PalazziandTeng Ma 329ffc89b9 [Mooncake] Fix silent SSD offload corruption when TP/PP ranks share ssd_offload_path (#31926) 
Signed-off-by: Michele Palazzi <sysdadmin@m1k.cloud>
Co-authored-by: Teng Ma <sima.mt@alibaba-inc.com>
 2026-09-17 10:51:03 +08:00
Meng, HengyuJuan MunetonYangKai0616devan-carlinAshwini RathiRanjan DebnathJuan MunetonAmrutha M
 		84d7604b7e [XPU] weekly simple model enablement 2026/09/14 (#39439) 
Co-authored-by: Juan Muneton <102537701+jmunetong@users.noreply.github.com>
Co-authored-by: YangKai0616 <kai.yang@intel.com>
Co-authored-by: devan-carlin <devan-carlin@users.noreply.github.com>
Co-authored-by: Ashwini Rathi <arathi@habana.ai>
Co-authored-by: Ranjan Debnath <ranjan.debnath@intel.com>
Co-authored-by: Juan Muneton <juan.muneton.gallego@intel.com>
Co-authored-by: Amrutha M <amrutha.m@intel.com>
 2026-09-17 10:43:04 +08:00
Aurick QiaoAurick QiaoKe Bao
 		4793f56835 [HiCache] Keep hybrid transfer layer maps stage-local under PP (#39699) 
Co-authored-by: Aurick Qiao <6137920+aurickq@users.noreply.github.com>
Co-authored-by: Ke Bao <ispobaoke@gmail.com>
 2026-09-17 10:18:44 +08:00
Yonghao ZhuangyhzhuangYJYJLee
 		0daa040e48 Support LongBench v2 in one-batch server benchmarks (#39874) 
Co-authored-by: yhzhuang <yhzhuang@fb.com>
Co-authored-by: YJYJLee <yejinlee@meta.com>
 2026-09-16 19:16:03 -07:00
qyb233 4fb9b5b5ba feat(hicache): support NPU Mamba states with FIA and async IO (#32500) 2026-09-17 10:12:26 +08:00
Shuwen Wang 4c85172f3a [HiCache] Back up MXFP8 KV scales in the host pool (#39089) 2026-09-17 09:40:26 +08:00
William Hu 0443e3179f fix(kda_prefill): fence shared writes before async proxy reads (#39124) 2026-09-16 18:37:19 -07:00
Xinyi Song 7780882f18 [AMD][bugfix] Fix dsv4 server launch (#39875) 2026-09-16 18:28:02 -07:00
Liangsheng YinBBufYuhao Yang
 		c89c63fa38 dsv4.1: vision tower and image preprocessing (#39668) 
Co-authored-by: BBuf <1182563586@qq.com>
Co-authored-by: Yuhao Yang <47235274+yhyang201@users.noreply.github.com>
 2026-09-16 18:11:16 -07:00
Liangsheng Yin 408d2334c3 dsv4.1: mHC computation and compensated projections (#39664) 
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
  Co-authored-by: BBuf <1182563586@qq.com>
  Co-authored-by: zijiexia <37504505+zijiexia@users.noreply.github.com>
 2026-09-16 17:11:55 -07:00
Liangsheng YinBBufYuhao Yang
 		46ae84df15 dsv4.1: Hopper FP8 matmul kernels and tuning (#39657) 
Co-authored-by: BBuf <1182563586@qq.com>
Co-authored-by: Yuhao Yang <47235274+yhyang201@users.noreply.github.com>
 2026-09-16 16:54:19 -07:00
Liangsheng Yin dc067c7d8c [Fix] Allow closed object schemas in Outlines prevalidation (#39869) 2026-09-16 16:42:17 -07:00
Liangsheng YinDarkSharpnessXiaoyu Zhang
 		c2443458e1 dsv4.1: RoPE and FP4 packing kernels (#39656) 
Co-authored-by: DarkSharpness <2040703891@qq.com>
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
Co-authored-by: BBuf <1182563586@qq.com>
 2026-09-16 16:17:12 -07:00
William Arnoldandishandhanani f45aad44bd [gRPC] Expose native pause status (#37488) 
Co-authored-by: ishandhanani <82981111+ishandhanani@users.noreply.github.com>
 2026-09-16 15:16:52 -07:00
Liangsheng YinDarkSharpnessXiaoyu Zhang
 		35b7589e1a dsv4.1: candidate indexer library (#39671) 
Co-authored-by: DarkSharpness <76582120+DarkSharpness@users.noreply.github.com>
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
 2026-09-16 15:15:18 -07:00
Liangsheng YinBBufClaude Opus 5DarkSharpness
 		13d593b6cf dsv4.1: compression, KV I/O, and metadata kernels (#39652) 
Co-authored-by: BBuf <1182563586@qq.com>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Co-authored-by: DarkSharpness <76582120+DarkSharpness@users.noreply.github.com>
 2026-09-16 13:54:07 -07:00
Justin Perlman 869674b3a7 [Fix] Prevalidate JSON Schema support per grammar backend (#37839) 2026-09-16 13:10:15 -07:00
Xinyuan Tong f0bf652534 Add Ling-3.0-flash-VL model support (#38526) 2026-09-17 00:19:26 +08:00
cctry 1b78083b42 [PD] Add optional KV transfer checksums (#39500) 2026-09-16 23:53:30 +08:00
AMD-yanfeiwangandDuyi-Wang a813224e78 [ROCm][DSV4] Enable breakable CUDA graph prefill (#37810) 
Co-authored-by: Duyi-Wang <duyi.wang@amd.com>
 2026-09-16 08:52:11 -07:00
ymren cc171fbad0 feat: support custom OTLP trace service name (#35802) 2026-09-16 22:37:42 +08:00
pllimax 00a9a81b67 [NPU][CI] Fail fast and speed up long-running qwen3.6 accuracy cases (#39813) 2026-09-16 20:20:37 +08:00
ShunkangzandZhangheng e7f7447333 [kv-shard 2/4] Sharded pools (#37615) 
Co-authored-by: Zhangheng <hzh0425@apache.org>
 2026-09-16 19:22:23 +08:00
Aurick QiaoandAurick Qiao 7b7620774c Fix device context during NIXL backend initialization (#38774) 
Co-authored-by: Aurick Qiao <6137920+aurickq@users.noreply.github.com>
 2026-09-16 17:59:24 +08:00
inkcherryandDuyi-Wang a3bf25dc62 [AMD] Clamp MORI intranode grid GPUs (#39763) 
Co-authored-by: Duyi-Wang <duyi.wang@amd.com>
 2026-09-16 02:13:59 -07:00
+4
Liangsheng YinCheng WanClaude Opus 5CursorDarkSharpnessDarkSharpnessKe BaoKhoa PhamXiaoyu ZhangXiaoyu ZhangYuhao YangYuwei AnZhichen ZengZiyi Xu
 		7d5696b3a1 dsv4.1: communication kernels and wrappers (#39653) 
Co-authored-by: Cheng Wan <54331508+ch-wan@users.noreply.github.com>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
Co-authored-by: DarkSharpness <2040703891@qq.com>
Co-authored-by: DarkSharpness <76582120+DarkSharpness@users.noreply.github.com>
Co-authored-by: Ke Bao <ispobaoke@gmail.com>
Co-authored-by: Khoa Pham <khoa.pham@radixark.ai>
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
Co-authored-by: Xiaoyu Zhang <xiaoyu.zhang@radixark.ai>
Co-authored-by: Yuhao Yang <47235274+yhyang201@users.noreply.github.com>
Co-authored-by: Yuwei An <ayw.sirius19@gmail.com>
Co-authored-by: Zhichen Zeng <zczeng@uw.edu>
Co-authored-by: Ziyi Xu <ziyi.xu@radixark.ai>
 2026-09-16 02:09:40 -07:00
Bingxu Chen 5a0c1e21e9 [AMD] Preserve deterministic inference when Lean Attention is enabled (#37740) 2026-09-16 02:09:08 -07:00
Bingxu Chen 2cbfaefbf9 [AMD] Avoid the FP8 wo_a path when the weight is BF16 (#38453) 
Signed-off-by: bingxche <bingxche@amd.com>
 2026-09-16 01:57:15 -07:00
Liangsheng YinandBBuf fc5a979f21 [misc] Merge FlashInfer autotune caches across spec workers, pad MXFP4 TP shards, drop dead ngram attrs (#39678) 
Co-authored-by: BBuf <1182563586@qq.com>
 2026-09-16 01:50:29 -07:00
vstone-w 0e528dc9ff bugfix:fix unifiedcache c128 radix cache management (#39426) 2026-09-16 16:47:42 +08:00
Void 9c8d4641ff [Fix] Fix GLM5 mHC PP forward (#39720) 2026-09-16 00:32:53 -07:00
Jensen 5beb2fd552 [NPU] Avoid device synchronization in Ascend sampling (#39404) 2026-09-16 10:15:16 +03:00
+4
Liangsheng YinBBufCheng WanClaude Opus 5CursorDarkSharpnessDarkSharpnessKe BaoKhoa PhamXiaoyu ZhangYuhao YangYuwei AnZhichen ZengZiyi Xu
 		faaff1eca8 dsv4.1: Top-k kernels and candidate selection (#39648) 
Co-authored-by: BBuf <1182563586@qq.com>
Co-authored-by: Cheng Wan <54331508+ch-wan@users.noreply.github.com>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
Co-authored-by: DarkSharpness <2040703891@qq.com>
Co-authored-by: DarkSharpness <76582120+DarkSharpness@users.noreply.github.com>
Co-authored-by: Ke Bao <ispobaoke@gmail.com>
Co-authored-by: Khoa Pham <khoa.pham@radixark.ai>
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
Co-authored-by: Xiaoyu Zhang <xiaoyu.zhang@radixark.ai>
Co-authored-by: Yuhao Yang <47235274+yhyang201@users.noreply.github.com>
Co-authored-by: Yuwei An <ayw.sirius19@gmail.com>
Co-authored-by: Zhichen Zeng <zczeng@uw.edu>
Co-authored-by: Ziyi Xu <ziyi.xu@radixark.ai>
 2026-09-15 23:54:35 -07:00
Hank Han a64be2e430 [Kernel] Add H20 block-FP8 MoE configs for GLM-5.3-Flash EP4/EP8 (#38913) 2026-09-15 23:42:18 -07:00
Shuwen WangandZhangheng 6b33338242 [HiCache] Forward prefix metadata to v2 storage calls (#39567) 
Co-authored-by: Zhangheng <hzh0425@apache.org>
 2026-09-16 14:05:42 +08:00
Liangsheng Yin 91f691c490 dsv4.1: standalone kernels and Python wrappers (#39646) 2026-09-15 22:31:18 -07:00
Shangming CaiandClaude Opus 5 3f8eb35ead [PD] Do not admit intake-rejected requests to a PD handoff (#38935) 
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
 2026-09-16 12:44:49 +08:00
Dayananda VandClaude Opus 5 100e1cd0d9 [Fix] Spawn, don't fork, the benchmark server process (#34712) 
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
 2026-09-16 12:44:09 +08:00
Xinguo ZhuandAKatydid 4678536df6 [CPU] Add fp8_per_tensor_scaled_mm_cpu kernel (#32618) 
Co-authored-by: AKatydid <xinguojoe@gmail.com>
 2026-09-16 12:31:05 +08:00
Xiaoyu Zhang 444b29c932 [Diffusion] Clean up obsolete worker plumbing, dead helpers, and tests (#39293) 2026-09-16 12:11:45 +08:00
Xinyi Song 954bb6804a [AMD][bugfix] Fix DSV4 MTP crash (#39547) 2026-09-15 21:10:23 -07:00
Xiaoyu Zhang 537ac52c5b [SRT] Clean up no-op compiler pass, dead helpers, and migration tests (#39295) 2026-09-16 12:04:21 +08:00
Zhang, Jiejing 6331e43081 [AMD] Prefer HIP Top-K for GLM-5.x on ROCm (#39631) 2026-09-15 20:55:57 -07:00
chx96642264 5f6dd44edc [NPU] [bugfix] Fix undefined require_attn_tp_allgather (#39561) 2026-09-16 11:02:40 +08:00
Mohammad Miadh AngkadandMohammad Angkad 935cbf24ec Accept MXFP8 dispatch in FlashInfer A2A TRT-LLM MoE (#39613) 
Co-authored-by: Mohammad Angkad <mohammad.angkad@radixark.ai>
 2026-09-15 19:23:15 -07:00
Rahul Vijayaraghavan d4ad368ed9 [Intel XPU] Enable fused_moe_triton tuning on XPU and add tuned DeepSeek-OCR-2 configs (#28723) 2026-09-16 10:20:22 +08:00
Cao E f11cd8ab0e [XPU] Use torch scaled_mm for XPU block FP8 linear (#35605) 2026-09-16 10:10:31 +08:00
Yuxingwang-intelandMa Mingfei 2cb51f5d22 [CPU] [Diffusion] Add fused scale-shift and norm kernels for CPU (#33452) 
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
 2026-09-16 10:01:29 +08:00
Zhang, Jiejingandfanxingran f920be4b09 [AMD] GLM-5.2 NextN: cast draft fused MoE to per-channel FP8 (#39155) 
Co-authored-by: fanxingran <xingran.fan@amd.com>
 2026-09-15 18:56:48 -07:00
xiaobochen-amdJohnQinAMDJiejing Zhang
 		7eedd57ab0 [ROCm] Fix EAGLE spec-decode verify silently sampling greedy on HIP (#37134) 
Co-authored-by: JohnQinAMD <yanyuan.qin@amd.com>
Co-authored-by: Jiejing Zhang <jiejing.zhang@amd.com>
 2026-09-15 18:49:49 -07:00