 YAMY
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9cc7da2ab0
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[MegaMoE] Wire Qwen MoE blocks to DeepGEMM MegaMoE (MXFP4 and NVFP4 experts) (#38080)
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2026-09-19 16:00:38 -07:00 |
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3a64faa1f2
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Fix disagg PP MTP for GLM-5.2 (#39378)
Co-authored-by: Julien Lin <jullin@nvidia.com>
Co-authored-by: YAMY1234 <74099316+YAMY1234@users.noreply.github.com>
Co-authored-by: Yangmin Li <yangminl@nvidia.com>
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2026-09-19 13:55:07 -07:00 |
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Zhiqiang Xie
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7a6c652c77
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[HiCache] Auto-size the host pool to fit available host memory (#40135)
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2026-09-19 12:50:43 -07:00 |
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metamergebotandcctry
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9e5a62a767
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[Logprob] Serve input-logprob temporaries from CUDA-graph-pool dead space (#40038)
Co-authored-by: cctry <csycfl@gmail.com>
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2026-09-19 12:03:52 -07:00 |
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7b67a96640
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[DSV4] Chunk the indexer MQA logits by query rows under a free-memory budget (#39095)
Signed-off-by: Shiki Wu <shikiw@nvidia.com>
Co-authored-by: Baizhou Zhang <sobereddiezhang@gmail.com>
Co-authored-by: Yuwei An <ayw.sirius19@gmail.com>
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2026-09-19 11:53:20 -07:00 |
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993d1fccba
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[ROCm] Widen the HiCache JIT copy rounds and enable the K-only host pool (#37152)
Co-authored-by: Xiaobo Chen <xiaobche@smci355-ccs-aus-n05-33.prov.aus.ccs.cpe.ice.amd.com>
Co-authored-by: HAI <hixiao@gmail.com>
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2026-09-19 08:58:10 -07:00 |
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Xiaoyu Zhang
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7fac84b639
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[DSV4.1] Reduce mHC, metadata and small-batch router overhead (#39704)
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2026-09-19 19:51:21 +08:00 |
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DarkSharpnessandBBuf
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d1acbe0746
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[DSV4.1] Big fused wo_a quant (#39957)
Co-authored-by: BBuf <1182563586@qq.com>
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2026-09-19 19:46:53 +08:00 |
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Xiaoyu Zhang
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cb22f2451e
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[Cleanup] Deduplicate kernel tests, diffusion fixtures and benchmark helpers (#40265)
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2026-09-19 19:45:38 +08:00 |
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Xiaoyu Zhang
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0b0d2c257a
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[Fix] Repair CI fixtures and ROCm speculative tree device checks (#40325)
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2026-09-19 18:16:05 +08:00 |
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Cheng Wan
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567d5925fe
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Fix mxfp4 padding test stubbing an accessor the module no longer imports (#40308)
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2026-09-19 00:43:56 -07:00 |
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Cheng Wan
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3a5f52e144
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Record a process's placement at publish, not at group build (#40071)
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2026-09-18 23:52:37 -07:00 |
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Xiaoyu Zhang
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36aa8479ef
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[Test] Fix fusion-group mocks after runtime context migration (#40290)
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2026-09-19 14:45:16 +08:00 |
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Lianmin Zheng
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5d703de9e4
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[HiCache] Size MHA host pools from device row width (#40304)
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2026-09-18 23:37:58 -07:00 |
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Xiaozhu Mengandmxz
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111aeedd37
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[Runtime] Add decode CUDA graph hooks for eager logits processing (#40222)
Co-authored-by: mxz <mxz@fb.com>
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2026-09-18 23:27:03 -07:00 |
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677c1cbdc9
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[Metrics] Propagate idle gaps across all scheduler loops (#40004)
Co-authored-by: metamergebot <324680979+metamergebot@users.noreply.github.com>
Co-authored-by: Jialin Ouyang <Jialin.Ouyang@gmail.com>
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2026-09-18 22:42:00 -07:00 |
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8189e3896b
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[PD] Skip singleton transfer-status all-reduces (#40003)
Co-authored-by: Pranjal Shankhdhar <pranjalssh@users.noreply.github.com>
Co-authored-by: Jialin Ouyang <Jialin.Ouyang@gmail.com>
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2026-09-18 22:41:50 -07:00 |
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5e9342d16f
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[PP][DeepSeek V4] Overlap communication and optimize SM120 prefill (#38792)
Co-authored-by: Yangmin Li <yangminl@nvidia.com>
Co-authored-by: YAMY <74099316+YAMY1234@users.noreply.github.com>
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2026-09-18 21:18:04 -07:00 |
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929230a6f0
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Fix GLM-OCR MTP multimodal embeddings and positions (#39088)
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
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2026-09-18 21:10:04 -07:00 |
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Vincent Liu
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090263eff6
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[VLM] avoid CUDA placement on non-CUDA platforms (#38750)
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2026-09-19 11:13:22 +08:00 |
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Xiaoyu Zhang
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986959e3c4
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[Refactor] Deduplicate kernel helpers and remove unused code (#40197)
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2026-09-19 09:27:30 +08:00 |
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Khoa PhamandCursor
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10b0bcfd18
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[PD] Allow decode radix cache and HiCache L1/L2 with DCP (#40263)
Co-authored-by: Cursor <cursoragent@cursor.com>
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2026-09-18 17:54:35 -07:00 |
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Liangsheng Yin
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d507accadc
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[Test] Drop dead and strictly-subsumed CI test registrations (#40264)
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2026-09-18 17:49:13 -07:00 |
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Cheng Wan
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fa7e83fd09
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Name the two widths of the WORLD group (#40070)
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2026-09-18 17:47:02 -07:00 |
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Cheng Wan
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81421b91e9
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One read path for every parallel name (#40069)
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2026-09-18 17:43:56 -07:00 |
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Cheng Wan
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afe71f4b9e
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Read process groups through the runtime context (#40068)
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2026-09-18 17:40:32 -07:00 |
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5931fd60ee
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Support unified memory page-envelope transfers in PD (#39477)
Co-authored-by: yhzhuang <yhzhuang@fb.com>
Co-authored-by: Lianmin Zheng <lianminzheng@gmail.com>
Co-authored-by: Yonghao Zhuang <yhzhuang@users.noreply.github.com>
Co-authored-by: Cheng Wan <cheng.wan@radixark.ai>
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2026-09-18 17:39:50 -07:00 |
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Cheng Wan
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d0730a0e8b
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Give the attention-DP width and rank one home (#40067)
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2026-09-18 17:34:33 -07:00 |
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Lifan Shen
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8ea0ee300d
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perf(sampling): avoid GPU syncs when applying custom logit processors (#39234)
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2026-09-18 17:09:30 -07:00 |
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Alison ShaoandXinyuan Tong
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21e6c98ccb
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Fix corrupted chat prompts on mistral_common tokenizers (tool_choice auto never fires) (#39773)
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
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2026-09-18 16:12:06 -07:00 |
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2394b231c2
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Fix Mistral3 retaining every vision-tower layer to read one (#39185)
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
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2026-09-18 16:11:54 -07:00 |
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Zhiqiang Xieandcctry
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ceb1d2e580
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[PD] Enable optimistic prefill with buffer-only L3 write-through HiCache (#40043)
Co-authored-by: cctry <csycfl@gmail.com>
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2026-09-18 16:04:15 -07:00 |
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5e4b94b134
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[MM] Skip VMM error gathers for text-only requests (#40005)
Co-authored-by: metamergebot <324680979+metamergebot@users.noreply.github.com>
Co-authored-by: Jialin Ouyang <Jialin.Ouyang@gmail.com>
Co-authored-by: Lianmin Zheng <lianminzheng@gmail.com>
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2026-09-18 16:00:43 -07:00 |
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Jialin Ouyang
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f3851486cb
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[Perf] Fuse SWA page lookup and mapping clear (#38948)
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2026-09-18 15:51:07 -07:00 |
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81a199f56a
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[HiCache] Read the in-flight buffer backup's node id from its snapshot in sanity_check (#40013)
Co-authored-by: Pranjal Shankhdhar <pranjalssh@meta.com>
Co-authored-by: Jialin Ouyang <Jialin.Ouyang@gmail.com>
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2026-09-18 15:47:56 -07:00 |
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0e5347db82
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Support MXFP8 and deferred route weighting in DeepEP v2 (#40030)
Co-authored-by: metamergebot <324680979+metamergebot@users.noreply.github.com>
Co-authored-by: Xingyu Liu <38244988+charlotte12l@users.noreply.github.com>
Co-authored-by: pranjalssh <14260275+pranjalssh@users.noreply.github.com>
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2026-09-18 15:40:38 -07:00 |
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Liangsheng Yin
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6cc9090d1f
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[mem_cache] Release up to owned_kv_len on radix cache insert (#40075)
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2026-09-18 15:37:52 -07:00 |
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Zhiqiang Xie
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a0534f8cca
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[HiCache] Stop arming a prefetch retry for a too-short storage span (#40042)
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2026-09-18 15:33:58 -07:00 |
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Sam (Kesen Li)
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d346b214fb
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feat(kv-cache): support SM100 NVFP4 GenMHA and speculative decoding (#36340)
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2026-09-18 14:50:46 -07:00 |
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metamergebotandcctry
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6a9c7001d3
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[Logprob] Borrow graph-pool memory for input logprob logits construction (#40007)
Co-authored-by: cctry <csycfl@gmail.com>
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2026-09-18 13:18:01 -07:00 |
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Jialin Ouyang
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da2f434951
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[Spec] Add explicit prefill shared-read capability for plugins (#39502)
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2026-09-18 13:11:01 -07:00 |
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Lianmin Zhengandraghotham
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248c202b46
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Use runtime token widths for Triton speculative verification (#39859)
Co-authored-by: raghotham <853234+raghotham@users.noreply.github.com>
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2026-09-18 11:07:55 -07:00 |
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Lianmin Zheng
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6bd1a0af1d
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Add registration for external model configurations (#39452)
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2026-09-18 10:06:24 -07:00 |
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81363bf8cb
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[kernel] Share the warp vectorized copy and enforce its alignment (#36176)
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Co-authored-by: BBuf <1182563586@qq.com>
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2026-09-18 22:40:54 +08:00 |
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a6cf05817f
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dsv4.1: remaining model and runtime integration (#38798)
Co-authored-by: BBuf <1182563586@qq.com>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Co-authored-by: Xiaoyu Zhang <xiaoyu.zhang@radixark.ai>
Co-authored-by: Yuwei An <ayw.sirius19@gmail.com>
Co-authored-by: Khoa Pham <khoa.pham@radixark.ai>
Co-authored-by: Yuhao Yang <47235274+yhyang201@users.noreply.github.com>
Co-authored-by: Zhichen Zeng <zczeng@uw.edu>
Co-authored-by: Ke Bao <ispobaoke@gmail.com>
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2026-09-18 02:55:30 -07:00 |
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Liangsheng Yin
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1b200ffaaa
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[Quant] Serve 32-wide-K ue8m0 block-FP8 linears through the FlashInfer MXFP8 GEMMs (#40039)
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2026-09-18 02:51:12 -07:00 |
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Shu Wang
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1e8699fda3
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[NVIDIA][comm] Merge EP+MoE-TP post-experts all-reduces into one _TP reduction (#32963)
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2026-09-18 01:35:10 -07:00 |
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zhaozx-cn
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8ac39c66d8
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[NPU] support kimi k3 on A5 and improve performance (#39589)
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2026-09-18 16:33:54 +08:00 |
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Rumit DesaiandXiaoyu Zhang
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1fdd6c8921
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[Runtime] Let out-of-tree platforms provide full graph backends (#37969)
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
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2026-09-18 15:42:46 +08:00 |
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iridiumine
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f86f60081d
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[NPU] Adapt hicache for K3 hybrid models (#39415)
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2026-09-18 14:48:20 +08:00 |
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