 Ma Mingfei
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073b36853f
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[CPU] update fla.cpp to support when num_head_v is not multiples of 16 (#30604)
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2026-07-10 09:21:07 +08:00 |
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Mick
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5ce5e1ee3e
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[Diffusion] Revert CPU AMX optimizations (#30716)
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2026-07-10 09:09:38 +08:00 |
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Ma Mingfei
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fdf6c70e3a
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fix arm test_norm.py error (#30597)
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2026-07-09 14:36:45 +08:00 |
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Haotong ZouandValentine233
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3b43df5b6d
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Support speculative decoding on CPU (#27862)
Co-authored-by: Valentine233 <xuan.liao@intel.com>
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2026-07-09 10:27:09 +08:00 |
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jianan-guandMa Mingfei
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177c048c68
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[Diffusion][CPU] Adding AMX optimizations for CPU platform (#28527)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
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2026-07-09 10:26:22 +08:00 |
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Xiaoyu ZhangandClaude Opus 4.8
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1da7d3a50b
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[MoE] Retire the AOT moe_fused_gate / kimi_k2_moe_fused_gate gate kernels (#26771) (#29997)
Co-authored-by: Claude Opus 4.8 <noreply@anthropic.com>
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2026-07-07 13:53:17 +08:00 |
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9bd02dc5b9
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feat(sgl-kernel): add InfLLM v2 attention kernels (#29383)
Co-authored-by: Size Wang <paulgeorge13hhhhh@gmail.com>
Co-authored-by: lijiayi <lijiayi@modelbest.cn>
Co-authored-by: suhmily10 <suhmily@gmail.com>
Co-authored-by: Xiaoyue Xu <xiaoyue.xu.me@gmail.com>
Co-authored-by: hansjohn <74091612+hansjohn@users.noreply.github.com>
Co-authored-by: zhangyan <1762895426@qq.com>
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2026-07-06 22:46:54 -07:00 |
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Ma Mingfei
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30fb0dd851
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[CPU] add fused_qk_gemma_norm and refactor norm kernel implementation (#30216)
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2026-07-07 08:52:59 +08:00 |
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Daniel Stokes
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8ee200972e
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[fix] Add support for flashinfer MOE A2A to Qwen3 BF16 model path (#26255)
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2026-07-01 01:59:54 -07:00 |
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Ma Mingfei
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bd3b252e0a
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[CPU] use faster exp in silu_and_mul (#29382)
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2026-06-29 09:38:30 +08:00 |
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Ma Mingfei
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3217410cf6
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[CPU] enable fused_sigmoid_mul on CPU device (#29378)
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2026-06-29 09:38:04 +08:00 |
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714011a40f
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[JIT Kernel] Migrate dsv3_router_gemm from AOT sgl-kernel to JIT kernel (#21531)
Co-authored-by: Guohao Shao <shao.gh.98@gmail.com>
Co-authored-by: Brayden Zhong <brayden@radixark.ai>
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2026-06-26 11:52:18 -07:00 |
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Yibo Cai
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4b0b0ea55f
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[sgl-kernel/cpu]: exclude amx gemm source from arm build (#29286)
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2026-06-26 08:23:43 +08:00 |
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Yibo Cai
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4ce1c180bd
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[sgl-kernel/cpu]: fix arm64 w8a8 moe kernel signature (#29270)
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2026-06-26 08:11:57 +08:00 |
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Ma Mingfei
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1ba7c79761
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[CPU] add indices in chunk_gated_delta_rule (#29267)
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2026-06-26 07:51:07 +08:00 |
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Ma Mingfei
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2c3f007a65
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[CPU] optimize GDN prefill performance (#29117)
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2026-06-25 09:04:34 +08:00 |
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Baizhou ZhangandShijin
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4b817f5d7f
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Upgrade fa3 hash (#28394)
Co-authored-by: Shijin <dovis.zhang02@gmail.com>
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2026-06-17 13:32:11 -07:00 |
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c2eae96c56
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MSCCL++ Integration (#22734)
Co-authored-by: Caio Rocha <caiorocha@microsof.com>
Co-authored-by: empyreus <rjsouza1995@gmail.com>
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2026-06-08 21:13:13 -07:00 |
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Zaili WangandMa Mingfei
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512bfbb1e1
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[CPU] Explicitly enable AVX512 & AMX instruction set (#26145)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
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2026-06-03 13:40:41 +08:00 |
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Mengxuan Xiong
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ff642ed936
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[MoE] Extend kimi_k2_moe_fused_gate to support 256 experts (MiMo V2 Flash) (#26303)
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2026-06-01 16:03:58 +08:00 |
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blzheng
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a722b1a437
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[CPU] fix incorrect index of b_ptr in fused_sigmoid_gating_delta_rule… (#26634)
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2026-05-29 16:08:12 +08:00 |
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3ecf2c76ad
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[CPU] Add GPT-OSS model optimization for CPU (#16775)
Co-authored-by: mingfeima <mingfei.ma@intel.com>
Co-authored-by: jianan-gu <jianan.gu@intel.com>
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2026-05-29 16:05:26 +08:00 |
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Aditya SharmaandXiaodong Ye
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b2eed9e16d
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[Apple Silicon] Add custom Metal RoPE kernel with fused KV cache store (#22868)
Signed-off-by: Xiaodong Ye <yeahdongcn@gmail.com>
Co-authored-by: Xiaodong Ye <yeahdongcn@gmail.com>
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2026-05-29 15:09:33 +08:00 |
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Chunyuan WU
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714fdd9723
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Fix MiniMax-M2.7 on CPU (#25061)
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2026-05-28 10:53:13 +08:00 |
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Chunan Zeng
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b66f8e0b96
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Sgl flashmla (#26132)
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2026-05-26 12:00:23 -07:00 |
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+2
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3f5e2c7688
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[AMD] Dsv4/pr2 compressor opt (#26208)
Co-authored-by: wunhuang <wunhuang@amd.com>
Co-authored-by: Thomas Wang <1am9trash@gmail.com>
Co-authored-by: Xinyi Song <86638975+RolaoDenthu@users.noreply.github.com>
Co-authored-by: HaiShaw <hixiao@gmail.com>
Co-authored-by: amd-danli103 <danli103@amd.com>
Co-authored-by: Lin, Soga <soga.lin@amd.com>
Co-authored-by: Raiden-Makoto <Raiden-Makoto@users.noreply.github.com>
Co-authored-by: Hubert Lu <55214931+hubertlu-tw@users.noreply.github.com>
Co-authored-by: yichiche@amd.com <jacky.cheng>
Co-authored-by: yctseng0211 <yctseng@amd.com>
Co-authored-by: Bingxu Chen <bingxche@amd.com>
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2026-05-25 23:54:40 -07:00 |
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Jincong Chen
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e27d4fb70f
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[Perf][Qwen3.5] Add case 512 to topkGatingSoftmaxKernelLauncher, (#25775)
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2026-05-25 16:08:21 +08:00 |
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Ma Mingfei
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821d5f4a5b
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[CPU] add faster KV-cache writes (#25874)
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2026-05-25 10:28:52 +08:00 |
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+2
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af8f66940e
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[AMD] Dsv4/pr1 fix run time issue (#25898)
Co-authored-by: wunhuang <wunhuang@amd.com>
Co-authored-by: Thomas Wang <1am9trash@gmail.com>
Co-authored-by: Xinyi Song <86638975+RolaoDenthu@users.noreply.github.com>
Co-authored-by: HaiShaw <hixiao@gmail.com>
Co-authored-by: amd-danli103 <danli103@amd.com>
Co-authored-by: Lin, Soga <soga.lin@amd.com>
Co-authored-by: Raiden-Makoto <Raiden-Makoto@users.noreply.github.com>
Co-authored-by: Hubert Lu <55214931+hubertlu-tw@users.noreply.github.com>
Co-authored-by: yichiche@amd.com <jacky.cheng>
Co-authored-by: yctseng0211 <yctseng@amd.com>
Co-authored-by: Bingxu Chen <bingxche@amd.com>
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2026-05-23 16:04:14 -07:00 |
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84ea47eb22
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[CPU] Fix issues when running llama3.2-11B vision model with image tasks (#8666)
Co-authored-by: JieXin Liang <Alcanderian@users.noreply.github.com>
Co-authored-by: Yineng Zhang <me@zhyncs.com>
Co-authored-by: jianan-gu <jianan.gu@intel.com>
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2026-05-21 13:09:18 +08:00 |
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Yuan Luoandluoyuan.luo
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b7085d3860
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[fp8] SM90 swap-AB scaled_mm dispatch (~1.16x kernel geomean, +5.8-18.5% end-to-end) (#25532)
Co-authored-by: luoyuan.luo <luoyuan.luo@antgroup.com>
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2026-05-20 13:20:37 +08:00 |
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miamiaoxyzandMa Mingfei
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5147de26e4
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Fix AMX GQA extend attention (#25180)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
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2026-05-18 09:30:02 +08:00 |
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nohup
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34cb8e2842
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fix(sgl-kernel): sm90 compile flashmla failed (#24130)
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2026-05-15 16:42:33 +08:00 |
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897587b03a
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[MUSA]: Add flashinfer sampling backend (#24978)
Co-authored-by: github-actions[bot] <github-actions[bot]@users.noreply.github.com>
Co-authored-by: zhiguo.qin <zhiguo.qin@mthreads.com>
Co-authored-by: R0CKSTAR <yeahdongcn@gmail.com>
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2026-05-14 20:23:15 -07:00 |
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R0CKSTAR
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74d70af09a
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[Apple Silicon] Add Metal kernel support in sgl-kernel (#23449)
Signed-off-by: Xiaodong Ye <yeahdongcn@gmail.com>
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2026-05-11 17:54:27 -07:00 |
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Brayden Zhongandb8zhong
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05d1ab51e8
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Enable PDL for various kernels in DSV32/GLM5 (#23965)
Co-authored-by: b8zhong <b8zhong@users.noreply.github.com>
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2026-05-09 03:42:56 -07:00 |
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Yuxuan Zhang
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d49fc092cb
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[Bug Fix] GLM-5.1: drop constexpr on page_indice_batch_offset, skip offloader post_init on draft worker, support N=32 in copy_to_gpu_no_ce (#23550)
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2026-05-09 15:43:45 +08:00 |
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Yibo Cai
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55d8223c2b
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[sgl-kernel/cpu] support w8a8 int8 model for arm cpu (#16045)
skip gpu test as this one is not related to gpu backend.
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2026-05-08 14:47:06 +08:00 |
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JoeyandR0CKSTAR
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15e6572f21
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[MUSA][18/N] Add MUSA-optimized kernel implementations for hot ops (#23255)
Signed-off-by: Joey-gvwal <joey_gvwal@yeah.net>
Co-authored-by: R0CKSTAR <yeahdongcn@gmail.com>
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2026-05-07 20:38:33 -07:00 |
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Mandepudi Rani ChowdaryandMa Mingfei
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55224fff08
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Add Arm64 CPU Phase 1A CI bootstrap (#22123)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
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2026-05-08 09:28:23 +08:00 |
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10fd0faccd
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[CPU] Add Qwen3.5 model optimization for CPU (#19484)
Co-authored-by: Zheng, Beilei <beilei.zheng@intel.com>
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
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2026-04-26 10:12:36 -07:00 |
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Jia GuoandClaude Opus 4.6
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587fd15bd2
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perf: eliminate attention DtoD copy by passing pre-allocated output to FA (#21985)
Co-authored-by: Claude Opus 4.6 <noreply@anthropic.com>
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2026-04-24 12:05:16 -07:00 |
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Ma Mingfei
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23e4d381f0
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[CPU] remove RECORD_FUNCTION (#23528)
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2026-04-24 09:18:29 +08:00 |
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MARATRIXandAlex Nails
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74c2e5bacd
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[MUSA][8/N] Port CUDA kernels that are compatible with MUSA (#17946)
Signed-off-by: yafeng.li <yafeng.li@mthreads.com>
Co-authored-by: Alex Nails <alex.nails@radixark.ai>
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2026-04-23 18:04:58 -07:00 |
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jianan-guandMa Mingfei
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ad0fc88810
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[CPU] [Quantization] Add GPTQ/AWQ 4bits quantization support for CPU (#22685)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
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2026-04-22 13:34:02 -07:00 |
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Tarushii Goel
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3ebf066d13
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[sgl] update specdec sampling kernel to return valid token ID (#22643)
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2026-04-21 20:28:19 -07:00 |
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Ma Mingfei
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929e00eeab
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[CPU] expand the interface of shared_expert without scaling factor (#22933)
merge since this is CPU only change on sgl-kernel.
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2026-04-21 20:03:39 +08:00 |
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fe9b9b254b
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Fix segfault in cudaMemcpyBatchAsync on CUDA 13.0 (#23136)
Co-authored-by: Claude Opus 4.6 <noreply@anthropic.com>
Co-authored-by: Kangyan-Zhou <zky314343421@gmail.com>
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2026-04-20 12:20:22 -07:00 |
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0dcfae5553
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[CPU] Add gemma4_rmsnorm_cpu kernel (#22842)
Co-authored-by: Copilot <198982749+Copilot@users.noreply.github.com>
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
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2026-04-17 13:03:16 +08:00 |
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Chunyuan WUandMa Mingfei
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6c89214584
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[CPU][sgl-kernel] extend_attention_cpu and flash_attn_varlen_func: fix nan for large seq (#22434)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
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2026-04-17 13:01:01 +08:00 |
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