 Liangsheng Yin
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94ce940ff8
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[Bug] Include DSA variant in exact-bucket graph admission (#38992)
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2026-09-10 21:03:03 -07:00 |
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yuchengliu1andMa Mingfei
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480b14edad
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[xpu] install xpu-kernel by released wheel (#37394)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
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2026-09-11 10:47:27 +08:00 |
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ANSHUMAN TRIPATHYandMa Mingfei
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0fadad8933
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DFLASH support added for XPU (#32798)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
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2026-09-11 10:39:37 +08:00 |
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Miaomiao Jiang
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690428b470
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[XPU] Add xpu forward in Gemma3RMSNorm & Add test and benchmark for Gemma3RMSNorm (#36278)
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2026-09-11 10:32:25 +08:00 |
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Vignesh Sethuraman
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7e3ae15f73
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[AMD] aiter: honor per-layer softmax scale (#38754)
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2026-09-10 19:27:09 -07:00 |
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ANSHUMAN TRIPATHY
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3716e496ea
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Speculative Decoding support for intel_xpu attention backend on XPU target (#30548)
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2026-09-11 10:25:25 +08:00 |
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ANSHUMAN TRIPATHYandmingfeima
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2adb2e8485
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[XPU] Adapt device agnostic API usage (#32093)
Co-authored-by: mingfeima <mingfei.ma@intel.com>
|
2026-09-11 10:03:12 +08:00 |
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Siju Samuel
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67d3a2ea57
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[XPU] Make checkpoint_engine worker device-agnostic (#32382)
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2026-09-11 09:56:39 +08:00 |
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ad7f57c9ea
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[Responses] Fix empty-prompt routing for token-first chat encoders (kimi_k3, inkling) (#35486)
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
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2026-09-11 01:06:20 +00:00 |
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jasonjk-park
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9df72e8f5a
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Fix custom logit processor params when num_tokens_in_batch is used (#38730)
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2026-09-10 17:52:08 -07:00 |
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Alexandrandronnie_zheng
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d0035da34e
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[Diffusion][Refactor] Refactor and unify RoPE execution for DiT models using RotaryEmbedding based on CustomOp (#33555)
Co-authored-by: ronnie_zheng <zl19940307@163.com>
|
2026-09-11 08:31:05 +08:00 |
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Liangsheng Yin
|
41da06adca
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[Refactor] Generalize DeepSeek V4 compressed pool management (#38954)
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2026-09-10 17:29:03 -07:00 |
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Mohammad Miadh AngkadandMohammad Angkad
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52c191da52
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[Deps] Retire the CUDA 12 lane (#38404)
Co-authored-by: Mohammad Angkad <mohammad.angkad@radixark.ai>
|
2026-09-10 16:58:09 -07:00 |
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fae8cd84cb
|
Support NemotronH_Omni_Reasoning_V3 in SGLang (#35599)
Signed-off-by: Ryan Stewart <rystewart@nvidia.com>
Signed-off-by: rystewart-nvidia <rystewart@nvidia.com>
Co-authored-by: elvischenv <219235043+elvischenv@users.noreply.github.com>
Co-authored-by: Po-Han Huang (NVIDIA) <53919306+nvpohanh@users.noreply.github.com>
|
2026-09-10 16:57:22 -07:00 |
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cctry
|
203d7e812c
|
Fix KV-canary workspace accounting after graph capture (#38596)
|
2026-09-10 16:10:12 -07:00 |
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cctry
|
42bbaac259
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[metrics] Report logical prefill token counts (#38566)
|
2026-09-10 16:09:21 -07:00 |
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Liangsheng Yin
|
dc5f59c3a2
|
[Refactor] Clarify DeepSeek V4 metadata names for V4.1 (#38947)
|
2026-09-10 15:42:52 -07:00 |
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Pengyun Lin
|
d076eec427
|
[SM120] Use exact query-head widths for DeepSeek-V4 sparse MLA decode (#36655)
|
2026-09-10 15:40:17 -07:00 |
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paulzhang-tmandQiaolin-Yu
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bb15be6d79
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[Spec] Stage Inkling MTP draft metadata before verify (#38169)
Co-authored-by: Qiaolin-Yu <liin1211@outlook.com>
|
2026-09-10 15:32:19 -07:00 |
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paulzhang-tm
|
a63efd9056
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[Spec] Support large MTP batches in short-convolution metadata (#38558)
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2026-09-10 15:13:17 -07:00 |
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fd7743e0e1
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[Sampling] Support sampling masks with overlap scheduling (#36631)
Co-authored-by: ByronHsu <ByronHsu@users.noreply.github.com>
Co-authored-by: root <root@slurm-h200-208-179.slurm-compute.tenant-slurm.svc.cluster.local>
Co-authored-by: Byron Hsu <byron+per@periodiclabs.ai>
|
2026-09-10 14:52:44 -07:00 |
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YAMY
|
55b45cb45a
|
fix(qsa): dequantize FP8 cached prefixes in the sparse prefill kernels (#38855)
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2026-09-10 14:07:39 -07:00 |
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06dfe05d65
|
[Deps] Raise smg-grpc-servicer floor to >=0.9.0 to unbreak SMG E2E CI (#38801)
Co-authored-by: Kangyan Zhou <kangyan.zhou@radixark.ai>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
|
2026-09-10 13:55:36 -07:00 |
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a26273d668
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[AMD] Quantize the bf16 MTP draft experts online to MXFP4 for Qwen3.5 (#38748)
Co-authored-by: Zijie Chen <300606707+zijiecode@users.noreply.github.com>
Co-authored-by: jacky.cheng <yichiche@amd.com>
|
2026-09-10 13:00:41 -07:00 |
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|
James
|
209654c420
|
[NPU][Hicache] Optimize HiCache L2 IO with Memfabric acc_offload (#38826)
|
2026-09-11 00:23:36 +08:00 |
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Shuwen Wang
|
19b83b4b9d
|
[Radix Cache] Fix PureSWA tail release without insertion (#38349)
|
2026-09-10 23:55:48 +08:00 |
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Shuwen Wang
|
cc7e43ad22
|
[HiCache] Account for newly pinned ancestors in load-back quota (#38481)
|
2026-09-10 23:54:08 +08:00 |
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|
pllimax
|
92dffebe16
|
[NPU] Set DEEPEP_HYBRID_DEPLOYMENT for new DeepEP tests; switch glm5_2 to w8a8; tune nightly timeouts (#38775)
|
2026-09-10 23:32:54 +08:00 |
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Chengze Fan
|
12771786f2
|
[AMD] Restore AITER verify runtime sizing reverted by #34647 (#38575)
|
2026-09-10 05:57:47 -07:00 |
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Jialin Ouyang
|
908226fea2
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[Rust TreeCore] Support external cache linker (#37306)
|
2026-09-10 19:22:24 +08:00 |
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liupeng374
|
334e94d8ac
|
[NPU] fix pp 2 hang on npu (#38249)
|
2026-09-10 19:21:37 +08:00 |
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Mohammad Miadh AngkadandMohammad Angkad
|
dc2157dcd6
|
[JIT] Port the expert-pack MXFP4 kernels to load_jit and fix their launch limits (#38830)
Co-authored-by: Mohammad Angkad <mohammad.angkad@radixark.ai>
|
2026-09-10 17:50:51 +08:00 |
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MickandMick Qian
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c9c26d56b2
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[diffusion] docs: sync snapshot and minimax-h3 subblock features (#38784)
Co-authored-by: Mick Qian <mickqian@users.noreply.github.com>
|
2026-09-10 17:23:43 +08:00 |
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8a6ab89bf0
|
[AMD] Enable Fast Triton Sparse MLA backend (#30575)
Co-authored-by: clintg6 <7388379+clintg6@users.noreply.github.com>
Co-authored-by: HAI <hixiao@gmail.com>
|
2026-09-10 01:58:00 -07:00 |
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ashwini rathi
|
b23db06769
|
pyproject(xpu): drop human-eval git dep to unblock image build (#38824)
|
2026-09-10 16:24:43 +08:00 |
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1b77f498a0
|
[NVIDIA] Support flashinfer Mega Moe (#31470)
Co-authored-by: djns99 <40156487+djns99@users.noreply.github.com>
Co-authored-by: 云挚 <ningyunxiao.nyx@antgroup.com>
Co-authored-by: Yangmin Li <yangminl@nvidia.com>
Co-authored-by: Po-Han Huang (NVIDIA) <53919306+nvpohanh@users.noreply.github.com>
|
2026-09-10 00:22:47 -07:00 |
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Brayden ZhongandBrayden Zhong
|
c0b790cf7f
|
Delete cutlass_mla, non-Marlin GPTQ, AWQ AOT kernel, and Dual Chunk Flash Attention (#32114)
Co-authored-by: Brayden Zhong <brayden@radixark.ai>
|
2026-09-10 15:12:01 +08:00 |
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Brayden ZhongandBrayden Zhong
|
7152c14384
|
Fix DeepSeek-V4 routing: sqrtsoftplus underflow and unfloored renorm (#34459)
Co-authored-by: Brayden Zhong <brayden@radixark.ai>
|
2026-09-10 15:10:50 +08:00 |
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|
Shuwen Wang
|
058cca0192
|
[HiCache] Fix side pools to use resolved host allocator (#38350)
|
2026-09-10 14:28:20 +08:00 |
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DAI0818andPo-Han Huang
|
03e4c06589
|
Fix Qwen3.5 GDN multi-item scoring (#33922)
Co-authored-by: Po-Han Huang (NVIDIA) <53919306+nvpohanh@users.noreply.github.com>
|
2026-09-09 22:30:39 -07:00 |
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ashwini rathiandarathi-hlab
|
6ab6df54b9
|
Add missing test dependencies to pyproject.toml variants (#36098)
Co-authored-by: arathi-hlab <arathi.rajendran@intel.com>
|
2026-09-10 12:49:16 +08:00 |
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|
Cheng Wan
|
f1a512c51c
|
[Config] msgspec.Struct for the config tier (#38753)
|
2026-09-09 19:41:19 -07:00 |
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Cheng Wan
|
53dc77ff4e
|
[Config] One writer for the declaration stash; no exception to the write seal (#38752)
|
2026-09-09 19:22:06 -07:00 |
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|
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fd596a474c
|
[XPU][Fix] Pack device-pointer tables as uint64 to avoid 64-bit address overflow (#35051)
Co-authored-by: roopaksrivastav <roopak.srivastava@intel.com>
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
|
2026-09-10 10:12:18 +08:00 |
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|
Mick
|
7f0285093e
|
[diffusion] feat: spill large tensors over shared memory like numpy arrays (#38656)
|
2026-09-10 09:14:06 +08:00 |
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MickandMick Qian
|
ce555ed82a
|
[diffusion] refactor: refactor utility ownership and document helper placement (#38699)
Co-authored-by: Mick Qian <mickqian@users.noreply.github.com>
|
2026-09-10 09:11:01 +08:00 |
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|
LinyuanLi
|
3ff226ba8f
|
[NPU]Support GLM5.2 and FP8 DSA&Indexer kvcache for 950 (#38250)
|
2026-09-10 09:10:10 +08:00 |
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|
|
92d831d3d7
|
[AMD] Parallelize aiter spec-decode KV index building over token blocks (#37659)
Co-authored-by: Zijie Chen <300606707+zijiecode@users.noreply.github.com>
Co-authored-by: jacky.cheng <yichiche@amd.com>
|
2026-09-09 17:53:53 -07:00 |
|
|
|
880d6fa64d
|
[DSv4] Integrate TRT-LLM DSv4 Attention for SM100/103 (#30805)
Co-authored-by: Yangmin Li <yangminl@nvidia.com>
Co-authored-by: Po-Han Huang (NVIDIA) <53919306+nvpohanh@users.noreply.github.com>
|
2026-09-09 17:40:07 -07:00 |
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|
William Hu
|
0084030179
|
Add Opt-In for GLM-5.3 Flash breakable prefill CUDA graphs (#38522)
|
2026-09-09 17:02:08 -07:00 |
|