 Jensen
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5beb2fd552
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[NPU] Avoid device synchronization in Ascend sampling (#39404)
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2026-09-16 10:15:16 +03:00 |
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+4
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faaff1eca8
|
dsv4.1: Top-k kernels and candidate selection (#39648)
Co-authored-by: BBuf <1182563586@qq.com>
Co-authored-by: Cheng Wan <54331508+ch-wan@users.noreply.github.com>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
Co-authored-by: DarkSharpness <2040703891@qq.com>
Co-authored-by: DarkSharpness <76582120+DarkSharpness@users.noreply.github.com>
Co-authored-by: Ke Bao <ispobaoke@gmail.com>
Co-authored-by: Khoa Pham <khoa.pham@radixark.ai>
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
Co-authored-by: Xiaoyu Zhang <xiaoyu.zhang@radixark.ai>
Co-authored-by: Yuhao Yang <47235274+yhyang201@users.noreply.github.com>
Co-authored-by: Yuwei An <ayw.sirius19@gmail.com>
Co-authored-by: Zhichen Zeng <zczeng@uw.edu>
Co-authored-by: Ziyi Xu <ziyi.xu@radixark.ai>
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2026-09-15 23:54:35 -07:00 |
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Liangsheng Yin
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91f691c490
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dsv4.1: standalone kernels and Python wrappers (#39646)
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2026-09-15 22:31:18 -07:00 |
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Shangming CaiandClaude Opus 5
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3f8eb35ead
|
[PD] Do not admit intake-rejected requests to a PD handoff (#38935)
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
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2026-09-16 12:44:49 +08:00 |
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Dayananda VandClaude Opus 5
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100e1cd0d9
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[Fix] Spawn, don't fork, the benchmark server process (#34712)
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
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2026-09-16 12:44:09 +08:00 |
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Xinguo ZhuandAKatydid
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4678536df6
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[CPU] Add fp8_per_tensor_scaled_mm_cpu kernel (#32618)
Co-authored-by: AKatydid <xinguojoe@gmail.com>
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2026-09-16 12:31:05 +08:00 |
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Xiaoyu Zhang
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537ac52c5b
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[SRT] Clean up no-op compiler pass, dead helpers, and migration tests (#39295)
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2026-09-16 12:04:21 +08:00 |
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Rahul Vijayaraghavan
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d4ad368ed9
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[Intel XPU] Enable fused_moe_triton tuning on XPU and add tuned DeepSeek-OCR-2 configs (#28723)
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2026-09-16 10:20:22 +08:00 |
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Cao E
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f11cd8ab0e
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[XPU] Use torch scaled_mm for XPU block FP8 linear (#35605)
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2026-09-16 10:10:31 +08:00 |
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Yuxingwang-intelandMa Mingfei
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2cb51f5d22
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[CPU] [Diffusion] Add fused scale-shift and norm kernels for CPU (#33452)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
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2026-09-16 10:01:29 +08:00 |
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Zhang, Jiejingandfanxingran
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f920be4b09
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[AMD] GLM-5.2 NextN: cast draft fused MoE to per-channel FP8 (#39155)
Co-authored-by: fanxingran <xingran.fan@amd.com>
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2026-09-15 18:56:48 -07:00 |
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7eedd57ab0
|
[ROCm] Fix EAGLE spec-decode verify silently sampling greedy on HIP (#37134)
Co-authored-by: JohnQinAMD <yanyuan.qin@amd.com>
Co-authored-by: Jiejing Zhang <jiejing.zhang@amd.com>
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2026-09-15 18:49:49 -07:00 |
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Jinyan Yi
|
dbd7281b06
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fix(npu): fix hybrid KV transfer with PP prefill in PD disaggregation (#38402)
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2026-09-16 09:10:17 +08:00 |
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Zhiqiang Xie
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4e9e407d37
|
[HiCache] Label radix-cache metrics per rank and split the "shrunk" prefetch reason (#39280)
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2026-09-15 17:54:04 -07:00 |
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Siyuan ChenandYuwei An
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c9a8fba991
|
[DSV4][BCG] Optimize the heavy memory use of C4 Indexer when BCG is enabled (#36534)
Co-authored-by: Yuwei An <ayw.sirius19@gmail.com>
|
2026-09-15 17:23:11 -07:00 |
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Liangsheng Yin
|
0dabef3d30
|
[misc] Fix tool-call index, graph padded-row count, and prefill-graph input_embeds refresh (#39574)
|
2026-09-15 16:37:22 -07:00 |
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Lianmin Zheng
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b803cfa0c4
|
Add external multimodal processors to the Rust frontend (#39329)
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2026-09-15 15:38:47 -07:00 |
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|
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2929a39927
|
Use a shared byte budget for unified hybrid-SWA memory (#36729)
Co-authored-by: yhzhuang <yhzhuang@fb.com>
Co-authored-by: Cheng Wan <cheng.wan@radixark.ai>
|
2026-09-15 15:27:00 -07:00 |
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4da5599e93
|
Fix first-token metadata and reused attention-layer indexing (#39328)
Co-authored-by: Jinghui Zhang <jinghui@meta.com>
Co-authored-by: Lucia Fang <116399278+luccafong@users.noreply.github.com>
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2026-09-15 15:22:26 -07:00 |
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Liangsheng Yin
|
87c9f78e99
|
[Fix][PD] Give prefill and decode their own RDMA NICs in disaggregation tests (#39584)
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2026-09-15 15:07:42 -07:00 |
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Cheng Wan
|
406c9c71d8
|
[Feature] Support BF16 and batch-invariant inference with DeepEP v2 (#38160)
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2026-09-15 14:30:50 -07:00 |
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YAMY
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24874f90a3
|
[Test] Fix DeepGEMM batch invariance test output dtype (#39636)
|
2026-09-15 12:40:28 -07:00 |
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jasonjk-parkandjasonjk
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073fdf97cc
|
Generalize auxiliary outputs (#39164)
Co-authored-by: jasonjk <jasonjk@twshared0085.36.lco2.facebook.com>
|
2026-09-15 12:05:13 -07:00 |
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Zhiqiang Xie
|
7f5dd19256
|
[HiCache] Rework the buffer-mode storage prefetch pipeline and retry bookkeeping (#39283)
|
2026-09-15 10:48:49 -07:00 |
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Shangming CaiandClaude Opus 5
|
47a157f257
|
[CI][Disaggregation] Fix EADDRINUSE flake in test_disaggregation_dwdp_gpt_oss (#39611)
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
|
2026-09-15 23:05:05 +08:00 |
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Siyuan ChenandBJWang-ant
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832ec39cc0
|
[Intra-node PD][DSV4] Pack all layers into one batch for INTRA_NODE_NVLINK path (#38984)
Co-authored-by: BJWang-ant <wangbingjia.wbj@ant-intl.com>
|
2026-09-15 21:08:33 +08:00 |
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Po-Han Huang (NVIDIA)
|
a2a261963f
|
[CI] Fix SWA decode radix cache NIXL import (#39600)
|
2026-09-15 21:01:05 +08:00 |
|
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Yuxuan ZhangandXinyuan Tong
|
17ba2c2e7c
|
Support non-strict GLM47 tool calls with EBNF constraints (#38890)
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
|
2026-09-15 16:41:48 +08:00 |
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Liangsheng Yin
|
8565b11003
|
[misc] Trim redundant variants from the 8-gpu-h20 disaggregation test suite (#39544)
|
2026-09-15 01:24:46 -07:00 |
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Beihao ZhouandBrayden Zhong
|
37ebacb50f
|
[EPLB] Drop defensive getattr for ep_dispatch_algorithm (#31804)
Co-authored-by: Brayden Zhong <b8zhong@uwaterloo.ca>
|
2026-09-15 16:14:41 +08:00 |
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Bi XueandLianmin Zheng
|
df254b0a11
|
[profiler] Label draft-runner steps DRAFT and target verify VERIFY in step spans (#38630)
Co-authored-by: Lianmin Zheng <lianminzheng@gmail.com>
|
2026-09-15 00:57:05 -07:00 |
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Khoa Pham
|
e4a6b090f4
|
[CI] Run test_unified_radix_cache_kl_dcp on cutedsl_mla with bf16 KV cache (#39553)
|
2026-09-15 00:35:01 -07:00 |
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|
iridiumine
|
8a20062652
|
[NPU][Bugfix] Disable pinned memory to fix DeepSeek-V2 DP-attention hang (#39423)
|
2026-09-15 14:59:31 +08:00 |
|
|
Liangsheng Yin
|
860fa83a9f
|
[CI] Wait for a killed test server's GPU memory before the next launch (#39545)
|
2026-09-14 23:24:37 -07:00 |
|
|
Cui Lily
|
e687b8d6af
|
[CPU] Implement fused QK Norm and RoPE kernels (#37748)
Signed-off-by: Cui, Lily <lily.cui@intel.com>
|
2026-09-15 14:17:57 +08:00 |
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|
Khoa PhamandClaude Fable 5.1
|
2c37b90ad6
|
[Fix][DCP] Localize widened KV ids in MLA retraction CPU backup/restore (#39487)
Co-authored-by: Claude Fable 5.1 <noreply@anthropic.com>
|
2026-09-15 13:33:41 +08:00 |
|
|
|
ddd4600197
|
[Fix] HiCache startup ImportError on the pinned kernel wheel (#39516)
Co-authored-by: Mohammad Angkad <mohammad.angkad@radixark.ai>
Co-authored-by: Liangsheng Yin <hnyls2002@gmail.com>
Co-authored-by: hnyls2002 <lsyincs@gmail.com>
|
2026-09-14 22:31:19 -07:00 |
|
|
|
6c514ab025
|
Force reasoning mode for GLM-5.3 chat templates (#39227)
Co-authored-by: Brayden Zhong <b8zhong@uwaterloo.ca>
Co-authored-by: Mohammad Angkad <mohammad.angkad@radixark.ai>
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
|
2026-09-15 13:16:26 +08:00 |
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|
Yanbin Jiang
|
ebd37705e4
|
[PD][LoRA] Gate decode admission on adapter slots (#39332)
|
2026-09-15 13:11:04 +08:00 |
|
|
ishandhanani
|
3f871a246c
|
feat(agent sessions): attribute stored KV cache blocks to sessions (#37482)
Signed-off-by: Ishan Dhanani <ishandhanani@gmail.com>
|
2026-09-14 21:34:49 -07:00 |
|
|
Shangming Cai
|
4b186cfea5
|
[CI][PD] Skip the flaky decode HiCache file-backend disaggregation test (#39368)
|
2026-09-15 11:19:03 +08:00 |
|
|
Aurick QiaoandAurick Qiao
|
5dde6e8f02
|
Fix MegaMoE buffer allocation and caching for effective SM budgets (#39223)
Co-authored-by: Aurick Qiao <6137920+aurickq@users.noreply.github.com>
|
2026-09-15 10:24:02 +08:00 |
|
|
Yuan Luoandluoyuan.luo
|
99060191e7
|
[KDA] Support ReplaySSM ring-write in the fused chain-verify kernel (#36821)
Co-authored-by: luoyuan.luo <luoyuan.luo@antgroup.com>
|
2026-09-15 10:22:41 +08:00 |
|
|
JoeandXiaoyu Zhang
|
a23fd557ed
|
[Kernel] Add OOT dispatch for clamp position (#38687)
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
|
2026-09-15 10:22:21 +08:00 |
|
|
raghothamandLianmin Zheng
|
c0b8725f5a
|
Fix /model_info serialization when a config value is a class (#39237)
Co-authored-by: Lianmin Zheng <lianminzheng@gmail.com>
|
2026-09-14 17:10:44 -07:00 |
|
|
Yang Liuandyangliu991
|
276663a79d
|
[model-loader] Split weight loading from postprocessing (#34981)
Co-authored-by: yangliu991 <yangliu991@fb.com>
|
2026-09-14 17:10:19 -07:00 |
|
|
Lianmin Zheng
|
a2b4e8888f
|
Allow CUDA VMM feature transport with the Rust frontend (#39347)
|
2026-09-14 17:09:49 -07:00 |
|
|
AMD-yanfeiwang
|
0163f8ff74
|
[AMD] Fix registered HiCache host pointer aliases (#35233)
|
2026-09-14 15:49:05 -07:00 |
|
|
Baizhou Zhang
|
2fca6d69aa
|
bumping sgl-deep-gemm to 0.2.0 (#39371)
|
2026-09-14 15:30:31 -07:00 |
|
|
cctry
|
dad8c074e7
|
Scope prefetch cache state to the request attempt (#39318)
|
2026-09-14 15:03:03 -07:00 |
|