 HZYandZhangheng
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8a0863c728
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[HiCache] Add MLA host-dedup primitives (#36800)
Co-authored-by: Zhangheng <hzh0425@apache.org>
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2026-09-08 23:40:21 +08:00 |
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325ab245a1
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[DCP] Allow fi_a2a on single-node systems Blackwell without MNNVL fabric ( ex B200 B300) (#37767)
Co-authored-by: Hao Phan <htphan@nvidia.com>
Co-authored-by: Khoa Pham <khoa.pham@radixark.ai>
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2026-09-08 07:55:36 -07:00 |
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Liu Ziming
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beecfda314
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[observability] Fix missing e2e/decode/inference latency span attributes (#37789)
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2026-09-08 22:50:55 +08:00 |
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15ff470472
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[diffusion] chore: key the VAE decode-dtype store by module layout (#38496)
Co-authored-by: Mick Qian <mickqian@radixark.ai>
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
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2026-09-08 22:37:21 +08:00 |
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HZY
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a6b542813f
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fix(glm-5.2-nvfp4): bound Mooncake synchronous transfer batches (#32758)
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2026-09-08 22:14:33 +08:00 |
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SovietPowerandXiaoyu Zhang
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4df5df911b
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[Scheduler] Add HRRN schedule policy to significantly reduce TTFT (#32911)
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
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2026-09-08 22:14:03 +08:00 |
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Po-Han Huang (NVIDIA)
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5097f9ac95
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Disable Hopper GLM shared-expert fusion for modelopt_fp4 Marlin (#37325)
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2026-09-08 06:16:36 -07:00 |
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Xiaoyu Zhang
|
554f817948
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[Diffusion] Optimize LTX-2 QKNorm and split RoPE on Hopper (#38396)
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2026-09-08 19:05:02 +08:00 |
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88a9bfd1ff
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[diffusion] CI: add per-case timing tolerance for host-I/O-bound perf guards (#38457)
Co-authored-by: Mick Qian <mickqian@radixark.ai>
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
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2026-09-08 18:40:17 +08:00 |
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zijiecandZijie Chen
|
e634ba78a4
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[AMD] gfx950 assembly attention for EAGLE verify, draft extend and decode (#37465)
Co-authored-by: Zijie Chen <300606707+zijiecode@users.noreply.github.com>
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2026-09-08 03:10:09 -07:00 |
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amd-danli103
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141febf329
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[AMD] fix: use the hardware fp8 e4m3 convert on gfx950 (#37140)
Signed-off-by: amd-danli103 <danli103@amd.com>
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2026-09-08 03:01:53 -07:00 |
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775f17b07c
|
[diffusion] optimization: stream mapped weights on a shared host/device pool (#38441)
Co-authored-by: Mick Qian <mickqian@radixark.ai>
Co-authored-by: Claude Fable 5.1 <noreply@anthropic.com>
|
2026-09-08 17:52:52 +08:00 |
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vorapolsiloai
|
7edcdd5ae6
|
[AMD] Skip AITER FP8 ASM prefill when GQA is unsupported (#38467)
|
2026-09-08 02:49:47 -07:00 |
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Hank Han
|
ccfa120dae
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Fix DSA compression tail capacity for PD decode request slots (#38417)
|
2026-09-08 01:50:07 -07:00 |
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cen121212
|
f8f03910f2
|
【NPU】Support EAGLE when PP enabled in prefill nodes (#32207)
|
2026-09-08 15:45:36 +08:00 |
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Sage
|
5aab054ec8
|
[rust-server] fix p/d bootstrap across dp listeners (#36234)
|
2026-09-08 13:22:32 +08:00 |
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Shuwen Wang
|
61d501427d
|
fix: make dfs weight ordering iterative (#38313)
|
2026-09-08 05:10:22 +00:00 |
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Anupa Sajikumar
|
91a45ea37e
|
[Intel][XPU][LoRA] Enable LoRA on Intel XPU (#30345)
|
2026-09-08 12:46:41 +08:00 |
|
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Liwansiandsglang-npu-bot
|
92371e9887
|
PD disaggregation, isolated transfer, prefill OOM fixed. (#38094)
Co-authored-by: sglang-npu-bot <sglangnpu@163.com>
|
2026-09-08 11:44:35 +08:00 |
|
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Wuhen Duan
|
dfd9b5c2a4
|
[NPU] Enable non-greedy MTP sampling (#32495)
|
2026-09-08 11:18:01 +08:00 |
|
|
Liangsheng Yin
|
28ebede865
|
[mem_cache] Free hybrid SWA pages by one representative per page on page_size > 1 (#38159)
|
2026-09-07 20:15:54 -07:00 |
|
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Liangsheng Yin
|
b23d835048
|
[Scheduler] Unify per-iteration request intake into ingest_requests() (#38389)
|
2026-09-07 20:02:02 -07:00 |
|
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Xinguo Zhu
|
2bf04f3a67
|
[Diffusion][CPU] Enable MiniMax-H3 on Xeon CPU (#35147)
|
2026-09-08 10:56:42 +08:00 |
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Polisetty V R K Jyothendra Varma
|
cf35384fe4
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[Intel GPU] Add MLA support to Intel XPU Attention backend for Prefill (#35866)
Signed-off-by: P V R K Jyothendra Varma <polisetty.v.r.k.jyothendra.varma@intel.com>
|
2026-09-08 10:29:28 +08:00 |
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HZY
|
8656901504
|
[Fix][DSA] Bound prefill Triton specializations for page-table stride (#37093)
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2026-09-08 10:23:51 +08:00 |
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Chao Shiandhuangtingwei9988
|
e31e5319a0
|
HiCache: Reduce the number of all_reduce in check_hicache_events for PP (#37562)
Co-authored-by: huangtingwei9988 <huangtingwei.htw@antgroup.com>
|
2026-09-08 10:13:22 +08:00 |
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|
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fba967ed9c
|
[diffusion] Support diffusion decoder parallel tiling for LTX-2.5 (#36026)
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
Co-authored-by: Mick Qian <mickqian@users.noreply.github.com>
|
2026-09-08 10:01:06 +08:00 |
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|
Siju Samuel
|
2358916d5a
|
[Feature][Intel XPU] Add memory saver support for Intel XPU via upstream torch_memory_saver (#29935)
|
2026-09-08 09:38:51 +08:00 |
|
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qyb233
|
c72cae201e
|
[NPU] Fix ViT graph key layout handling (#37758)
|
2026-09-08 09:21:02 +08:00 |
|
|
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5aa913e156
|
[AMD][GLM-5.2] Keep GlmMoeDsa MoE e_score_correction_bias in fp32 (#37133)
Co-authored-by: JohnQinAMD <yanyuan.qin@amd.com>
Co-authored-by: Thomas Wang <thomawan@amd.com>
Co-authored-by: Zhang, Jiejing <jiejing.zhang@amd.com>
|
2026-09-07 18:17:54 -07:00 |
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Kamil
|
792543f98c
|
[Scheduler] Make request-timeout aborts rank-consistent to fix TP collective hangs (#37143)
|
2026-09-07 18:01:25 -07:00 |
|
|
Liangsheng Yin
|
4dcecc7891
|
Revert "[kernel] add fused silu mul quant fp8" (#38381)
|
2026-09-07 17:36:10 -07:00 |
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Ziang Li
|
20ca564bf7
|
Add zianglih as online NVFP4 and DSA Top-K code owner (#33624)
|
2026-09-07 16:08:11 -07:00 |
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|
Baizhou Zhang
|
85d39401c8
|
[CP V1 Deprecation 3.5/5] Deprecate HIP/NPU/MUSA prefill CP and remove legacy implementation (#38293)
|
2026-09-07 15:39:34 -07:00 |
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amd-danli103andThomas Wang
|
e9e9e37ddc
|
[AMD] Restore SWA reprefill-tail on UnifiedRadixCache when HiCache is off (#32759)
Co-authored-by: Thomas Wang <thomawan@amd.com>
|
2026-09-07 14:27:53 -07:00 |
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|
|
570087ceda
|
[AMD][DSV4] Reland unified-KV pool sizing and SWA ring accounting, fully gated (#38192)
Co-authored-by: hnyls2002 <lsyincs@gmail.com>
Co-authored-by: Liangsheng Yin <hnyls2002@gmail.com>
|
2026-09-07 13:13:04 -07:00 |
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|
jiaryang
|
6287ebf43a
|
[AMD] Fix EAGLE crash when no kv_index_translator is bound on the DSA fp8 read door (#38318)
|
2026-09-07 13:03:10 -07:00 |
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Mohammad Miadh AngkadandMohammad Angkad
|
a711785475
|
[Kernel] Drop the vendored dense BF16 GEMM port in favor of FlashInfer 0.6.18 (#38124)
Co-authored-by: Mohammad Angkad <mohammad.angkad@radixark.ai>
|
2026-09-07 12:59:33 -07:00 |
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|
|
bf68369a18
|
[ray] Support Ray metric backend for engine metrics (#31415)
Signed-off-by: Jeffrey Wang <jeffreywang@anyscale.com>
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Co-authored-by: Qiaolin Yu <liin1211@outlook.com>
|
2026-09-07 12:43:19 -07:00 |
|
|
Aurick Qiao
|
8392c36bce
|
[Bugfix][Mamba] Clear deferred init metadata before speculative decode (#37165)
|
2026-09-07 12:41:03 -07:00 |
|
|
Chan ahn
|
dcebe8c473
|
[Kernel] Add fused MoE Triton configs for Qwen3.8-Flash-Next FP8 on NVIDIA H200 NVL (TP2+EP2) (#38116)
|
2026-09-07 10:17:55 -07:00 |
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Brayden ZhongandBrayden Zhong
|
c99d906eff
|
Drop the routing bias casts in flashinfer trtllm MoE (#33591)
Co-authored-by: Brayden Zhong <brayden@radixark.ai>
|
2026-09-07 09:04:33 -07:00 |
|
|
|
f3ccd1c0e4
|
[diffusion] CI: baseline the e2e of ten unguarded perf cases (#38335)
Co-authored-by: Mick Qian <mickqian@radixark.ai>
Co-authored-by: Claude Fable 5.1 <noreply@anthropic.com>
|
2026-09-07 23:13:14 +08:00 |
|
|
zijiexiaandXinyuan Tong
|
b5c9b68f03
|
[Kimi-K3] Recover the reply when the model skips the think channel (#37743)
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
|
2026-09-07 14:08:42 +00:00 |
|
|
|
62a4a6ea0e
|
[NPU] Add NPU arch35 support and enhance DSV4 processing in DeepSeek-V4 (#37373)
Co-authored-by: AndyLi429 <AndyLi429@noreply.gitcode.com>
Co-authored-by: Kailong Lu <kelonlu@163.com>
Co-authored-by: cx <chengxin65@huawei.com>
Co-authored-by: ranjiewen <ranjiewen@huawei.com>
Co-authored-by: HEX1A0A <1a0ahex@gmail.com>
Co-authored-by: vstone-w <374330057@qq.com>
Co-authored-by: Even Zhou <even.y.zhou@outlook.com>
Co-authored-by: ClownBin <chaobin1993@126.com>
Co-authored-by: sglang-npu-bot <sglangnpu@163.com>
|
2026-09-07 21:08:06 +08:00 |
|
|
Shuwen Wangandhuangtingwei
|
df623d3cbd
|
fix: keep queued Mooncake linker loads after abort (#38195)
Co-authored-by: huangtingwei <141888744+huangtingwei9988@users.noreply.github.com>
|
2026-09-07 20:25:13 +08:00 |
|
|
Carrie ChenandBrayden Zhong
|
8ae962021d
|
Use fp32 in TRTLLM all reduce buffers (#36143)
Co-authored-by: Brayden Zhong <b8zhong@uwaterloo.ca>
|
2026-09-07 16:57:07 +08:00 |
|
|
BingjiaWang
|
861d40f3ee
|
Fix DSpark CUDA graph replay with MegaMoE TP attention (#34919)
|
2026-09-07 01:35:35 -07:00 |
|
|
Cheng Wan
|
b5766336d4
|
[Perf] Unified memory: close the DCP decode gap on Blackwell (#37926)
|
2026-09-07 01:10:44 -07:00 |
|
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lixiufei-leoandlixiufei-leo
|
a8edafff7c
|
[AMD][gfx95] DSV4 wo_b (dp-attention): route to tuned bpreshuffle GEMM instead of triton (#38227)
Co-authored-by: lixiufei-leo <lixiufei-leo@users.noreply.github.com>
|
2026-09-07 00:36:15 -07:00 |
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