 Liangsheng Yin
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a36c873147
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[misc] Remove unit test cases that fail the admission criteria (round 2) (#30703)
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2026-07-09 16:35:59 -07:00 |
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Liangsheng Yin
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c53559ba10
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[misc] Remove unit test cases that fail the admission criteria (#30690)
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2026-07-09 15:31:28 -07:00 |
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Spandan Tiwari
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40a522203c
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[Quantization][Bugfix]: Join multi-arg RuntimeError in Quark _check_scheme_supported (#25694)
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2026-07-09 15:07:14 -07:00 |
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Spandan Tiwari
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48d98b7c68
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[Quantization][bugfix] Correct E8M0 NaN-sentinel detection in e8m0_to_f32 (#25519)
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2026-07-09 15:02:53 -07:00 |
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Xinyuan Tong
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7132af28de
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Fix garbage output for bare-tekken Mistral checkpoints (e.g. Leanstral) (#30396)
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2026-07-10 00:08:38 +05:30 |
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Mohammad Miadh Angkad
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b0ecbceed9
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[Bugfix] Migrate retired parallel accessors (#30653)
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2026-07-09 11:22:34 -07:00 |
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26ba3458d3
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[AMD] Fix int32 offset overflow in Triton decode-attention kernels (#28788)
Co-authored-by: Chun Fang <chun.fang@amd.com>
Co-authored-by: HaiShaw <hixiao@gmail.com>
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2026-07-09 11:20:04 -07:00 |
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YAMY
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2e4d6368c3
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[GDN] Auto-select FlashInfer GDN prefill on validated SM100 configs (#29734)
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2026-07-10 00:26:00 +08:00 |
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cctryandcctry
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1959335997
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refactor(load-snapshot): build LoadSnapshot directly, drop legacy get_loads IPC (#30525)
Co-authored-by: cctry <cctry@fb.com>
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2026-07-09 05:58:10 -07:00 |
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fzyzcjy
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6ab7a65d94
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Support grad injection and step override in the dumper's model dump (#30657)
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2026-07-09 20:26:05 +08:00 |
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fzyzcjy
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5b28465eb9
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Cap diagnostic detail computation for failing tensors (#30656)
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2026-07-09 20:19:51 +08:00 |
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fzyzcjy
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287291c232
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Fix rel_diff being nan for bitwise-identical tensors (#30655)
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2026-07-09 20:16:18 +08:00 |
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fzyzcjy
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0d7e8cfb85
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Support per-regex diff-threshold predicates in the tensor comparator (#30654)
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2026-07-09 20:15:36 +08:00 |
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Lianmin Zheng
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a9e804623e
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Allow EPLB manual test to use FlashInfer A2A (#30641)
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2026-07-09 03:46:07 -07:00 |
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Shijin Zhang
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8e54517f02
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[Feat][GLM5.2] Add DSA Cache Layer Split under Prefill CP (#29421)
Signed-off-by: Shijin Zhang <75300765+Dovis01@users.noreply.github.com>
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2026-07-09 03:03:56 -07:00 |
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Cheng Wan
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c02b032da0
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[fix] Repoint the prefetch-dispatch test at the loader's current config binding (#30631)
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2026-07-09 02:21:04 -07:00 |
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Cheng Wan
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1f15308dca
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[refactor] Retire the legacy config accessor and the remaining process singletons (#30493)
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2026-07-09 02:10:47 -07:00 |
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Cheng Wan
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e703f9e566
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[refactor] Adopt get_parallel() everywhere and close out the parallel wrapper surface (#30492)
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2026-07-09 02:09:39 -07:00 |
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Cheng Wan
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06eb1b1838
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[refactor] Split the DP gathered-buffer state between flags.dp and ctx.forward (#30491)
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2026-07-09 02:09:21 -07:00 |
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Cheng Wan
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fef2128e19
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[refactor] Add the per-forward flags tier: ctx.forward (#30490)
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2026-07-09 02:09:03 -07:00 |
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Cheng Wan
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65b14881c5
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[refactor] Move the EP dispatcher and fusion-workspace manager state onto ctx.resources (#30489)
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2026-07-09 02:08:35 -07:00 |
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AMD-yanfeiwangandDuyi-Wang
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d74619b373
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[AMD] Enable JIT staged HiCache write-back and fix CPU-index crash (#28534)
Co-authored-by: Duyi-Wang <duyi.wang@amd.com>
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2026-07-09 01:22:37 -07:00 |
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Ata Fatahi
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866ae6848f
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[PDD] Add true request retraction for PDD (#25372)
Signed-off-by: Ata Fatahi <immrata@gmail.com>
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2026-07-09 15:33:01 +08:00 |
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Mohammad Miadh Angkad
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666a09fe2a
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Disable multi-threaded load by default when prefetch is on (#30146)
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2026-07-09 00:28:53 -07:00 |
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Liangsheng Yin
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64e2a73c80
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[Fix] Serialize FanOutCommunicator queueing calls with a FIFO-fair asyncio.Lock (#30606)
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2026-07-09 00:04:43 -07:00 |
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weireweireandweireweire
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1c9eb6bb0b
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[DSV4] Fix draft SWA transfer for disaggregated MTP (#30461)
Co-authored-by: weireweire <20922698+weireweire@users.noreply.github.com>
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2026-07-09 13:18:34 +08:00 |
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Haotong ZouandValentine233
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3b43df5b6d
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Support speculative decoding on CPU (#27862)
Co-authored-by: Valentine233 <xuan.liao@intel.com>
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2026-07-09 10:27:09 +08:00 |
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jianan-guandMa Mingfei
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177c048c68
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[Diffusion][CPU] Adding AMX optimizations for CPU platform (#28527)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
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2026-07-09 10:26:22 +08:00 |
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Michael
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cf8f1df6e8
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[AMD] add dedicated jit-kernel-benchmark-test-amd stage + register portable JIT benches (#30307)
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2026-07-08 18:09:05 -07:00 |
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Xinyuan Tong
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074bb928f0
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Move template manager files under parser; update CODEOWNERS (#26052)
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2026-07-08 16:47:36 -07:00 |
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Cheng WanandClaude Opus 4.8
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cc13e2eae7
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[CI] Move piecewise CUDA graph (pcg) tests to nightly (#30563)
Co-authored-by: Claude Opus 4.8 <noreply@anthropic.com>
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2026-07-08 16:07:08 -07:00 |
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cctry
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096551eed6
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Make CUDA graph disabling PD-role-aware (prefill/decode) (#30409)
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2026-07-08 15:08:22 -07:00 |
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Lianmin Zheng
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ca8f15cd70
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Fix FlashInfer A2A IMA by DP-synchronizing the decode graph bucket (#30242) (#30450)
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2026-07-08 14:34:49 -07:00 |
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Michael
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c55190a638
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[AMD] Register 2 CPU-bound 1-GPU tests (phase_checker, scripted_runtime_core) for AMD PR CI (#30446)
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2026-07-08 14:04:23 -07:00 |
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Michael
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47a6dfd708
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[AMD] Register 3 ROCm-portable JIT kernel tests for AMD CI (#30212)
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2026-07-08 13:38:17 -07:00 |
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Xinyuan TongandEazyReal
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45019b56ce
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[Bugfix] Map reasoning_effort=low to Nemotron-3 Super low_effort + warn on unsupported levels (#30463)
Co-authored-by: EazyReal <8047065+EazyReal@users.noreply.github.com>
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2026-07-08 12:19:44 -07:00 |
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sonle5andsunxxuns
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8d2b66fd90
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Fix gfx95 bpreshuffle FP8 activation scale layout (#29275)
Co-authored-by: sunxxuns <126995791+sunxxuns@users.noreply.github.com>
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2026-07-08 10:55:09 -07:00 |
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Xiaoyu Zhang
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b8ca06fdad
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Fix zero expert routed ids for MoE backends (#30387)
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2026-07-08 21:23:25 +08:00 |
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shuwenn
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108a183f6b
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[mem_cache][6/N] refactor: move MHA host-pool into pool_host/mha.py (#30249)
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2026-07-08 20:12:52 +08:00 |
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amote-i
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c9303a08da
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Fix scheduler crash on prefill-unreachable decode abort (#29834)
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2026-07-08 14:06:37 +08:00 |
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Cheng Wan
|
7709a1f358
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[refactor] ctx.resources: named slots, stream leases, and workspace buffer leases (#30348)
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2026-07-07 21:30:10 -07:00 |
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Cheng Wan
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b7cca0bf8f
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[refactor] Collect MoE and DP-attention runtime state into typed flag groups (#30347)
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2026-07-07 21:29:27 -07:00 |
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Cheng Wan
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be32c57598
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[refactor] Read resolved config from server_args fields; retire the flags mirror tier (#30346)
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2026-07-07 21:28:34 -07:00 |
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Cheng Wan
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b14f7b4f75
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[refactor] Move model-capability adjustments into the resolution pipeline (#30299)
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2026-07-07 21:26:55 -07:00 |
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7bc343470f
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[Spec] DFlash: support pure-MLA targets with an fp8 KV cache (Kimi-K2.x-NVFP4) (#29218)
Co-authored-by: Hao Phan <htphan@nvidia.com>
Co-authored-by: Claude Opus 4.8 <noreply@anthropic.com>
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2026-07-07 19:52:14 -07:00 |
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Yuchen Tian
|
9f5948c391
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feat(mem_cache): add client-side metadata cache for HiCacheFile storage (#29716)
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2026-07-07 18:21:46 -07:00 |
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d7dcdf3efd
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[DSV4] perf: Make FP8 quant output tensor contiguous (#27926)
Co-authored-by: liqichao <liqichao@baidu.com>
Co-authored-by: chenbong <bhchen@stu.xmu.edu.cn>
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2026-07-07 17:40:59 -07:00 |
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YAMY
|
48ad6a83cf
|
[DeepSeek-V4] Enable non-paged indexer by default for large prefill chunks (#30140)
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2026-07-07 15:51:24 -07:00 |
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Alex NailsandClaude Opus 4.7
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3d2e7cc601
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[gRPC] Native server: launcher + HTTP + server args wiring (3/4) (#23508)
Co-authored-by: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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2026-07-07 14:57:25 -07:00 |
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Michael
|
60f502a4fd
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[AMD] Register 2 hardware-agnostic 1-GPU PR tests for AMD CI (#30207)
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2026-07-07 14:46:22 -07:00 |
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