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64e404263e
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[Doc] Fix TP and attention-TP group layout in initialize_model_parallel docstring (#34862)
Co-authored-by: NanoByte0513 <167996578+NanoByte0513@users.noreply.github.com>
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
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2026-08-19 08:15:03 +08:00 |
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c14312a664
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[Spec] DFlash2: local convolution + candidate selector (#35371)
Co-authored-by: Jian Chen <jianchen0311@gmail.com>
Co-authored-by: Liangsheng Yin <hnyls2002@gmail.com>
Co-authored-by: hnyls2002 <lsyincs@gmail.com>
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2026-08-18 17:07:28 -07:00 |
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Baizhou Zhang
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cfc6dfb364
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Apply latest DeepEP branch (#34923)
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2026-08-18 16:24:50 -07:00 |
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cctryandcctry
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37c09ff3d8
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[Memory] Borrow CUDA graph pool storage for EAGLE sampling (#35375)
Co-authored-by: cctry <cctry@fb.com>
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2026-08-18 16:19:41 -07:00 |
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Liangsheng Yin
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7ebaa98f81
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[Fix] Assert the page-aligned SWA evict floor on both PD decode prealloc paths (#35396)
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2026-08-18 15:48:55 -07:00 |
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Liangsheng Yin
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87a09494fa
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[Refactor] Share the page-aligned decode alloc lens between EAGLE and DFLASH (#35382)
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2026-08-18 14:39:41 -07:00 |
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Joe Rowell
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7b5410c999
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Laguna: config-driven MoE router scoring (#35362)
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2026-08-18 13:42:36 -07:00 |
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Liangsheng Yin
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79dfef390b
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[Spec] Page-align the DFLASH decode KV reservation (#35265)
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2026-08-18 13:36:04 -07:00 |
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Liangsheng Yin
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aa82229173
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[Fix] Assert the page-aligned SWA evict floor at PD decode prealloc (#35286)
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2026-08-18 13:32:16 -07:00 |
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307a90f6d3
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Stop losing Kimi-K3 tool calls to reasoning, constraint conflicts, and truncation (#34881)
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
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2026-08-18 12:42:56 -07:00 |
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Wei YangandWei Yang
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8bb106cee9
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Fix NIXL cleaner grouping for hybrid cache keys (#35130)
Co-authored-by: Wei Yang <yawei@microsoft.com>
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2026-08-18 13:55:51 -05:00 |
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Hanming Lu
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526af15845
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[Metrics] Discount queued prefill load by recent cache hits when waiting-queue matching is off (#35248)
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2026-08-18 11:27:21 -07:00 |
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Xingyu Liuandxingyuliu
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7dcaf11987
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[Fix] Select custom all-reduce v2 by topology capability (#35061)
Co-authored-by: xingyuliu <xingyuliu@fb.com>
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2026-08-18 10:30:10 -07:00 |
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Ke Bao
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480033def0
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Refactor kv cache event mixin into a recorder (#35164)
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2026-08-19 01:20:17 +08:00 |
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jain-ria
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83d7d45330
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fix: preserve output logprobs without input logprobs (#34627)
Signed-off-by: jain-ria <riajain@NVIDIA.com>
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2026-08-18 12:07:13 -05:00 |
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MickandClaude Opus 5
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3f26febaff
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[diffusion] fix: decouple encoder parallelism from the dit parallel layout (#34713)
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
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2026-08-19 00:16:09 +08:00 |
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LinyuanLi
|
9485c083bb
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[NPU] Add mxfp4-w4a4 MOE Quantization Support for NPU (#30319)
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2026-08-18 19:06:05 +03:00 |
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Shangming CaiandClaude Opus 4.8
|
97dedd1ce9
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[PD] Deferred decode-side KV release for aborts mid-transfer (#35049)
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
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2026-08-18 23:56:33 +08:00 |
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pllimax
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499e90a125
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[NPU CI] Reorganize test output/log directory structure with workflow context (#33685)
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2026-08-18 23:46:00 +08:00 |
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|
WenhaoZhang
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63d783bbe0
|
[diffusion] optimization: INT8 Linear + pluggable DiT attention backends for MiniMax-H3 on consumer-level GPUs (#34581)
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2026-08-18 21:44:39 +08:00 |
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paulzhang-tm
|
0065fbfae1
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[Scheduler] Cap prefill-delayer queue target by admission capacity (#35191)
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2026-08-18 21:40:13 +08:00 |
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Andy Ye
|
94eef833fe
|
[diffusion] rl: support cosmos3 (#34197)
|
2026-08-18 20:42:27 +08:00 |
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Xiaoyu ZhangandClaude Opus 5
|
ae6945e112
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[kernels] Reorganize ops/diffusion by operator domain behind a lazy facade (#35114)
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
|
2026-08-18 20:37:43 +08:00 |
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YC Yen-Ching Tseng
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f7101b0ae6
|
[AMD] MiniMax-M3 : Fuse QKV+index proj for block-fp8 (#32099)
|
2026-08-18 03:01:01 -07:00 |
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karverma-amd
|
24d625698d
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[AMD] feat(moe): fold padded-topk_ids fill into fused shared-experts append+remap (#31370)
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2026-08-18 02:32:57 -07:00 |
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|
Lianmin Zheng
|
70ee6b1714
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[Rust Server] Add e2e latency metadata and fix Sarashina import (#35125)
|
2026-08-18 02:08:07 -07:00 |
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|
mohbasit
|
fc0b95e7ba
|
Profiling Enhancements [2/3]: detailed execution step annotations (#24911)
|
2026-08-18 01:09:07 -07:00 |
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Emil BogomolovandEmil Bogomolov
|
667389c50f
|
[diffusion] chore: filter transformer safetensors by index.json to drop duplicate shard variants (#35107)
Co-authored-by: Emil Bogomolov <zetyquickly@googlemail.com>
|
2026-08-18 16:05:05 +08:00 |
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Liangsheng Yin
|
0111b29031
|
[Perf] Hoist DSv4 draft-extend SWA write locs; unify SWA graph buffer naming (#34890)
|
2026-08-18 00:13:28 -07:00 |
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Lianmin Zheng
|
a779a2a2a5
|
[Chore] Move version tag helper to release scripts (#35196)
|
2026-08-18 00:11:12 -07:00 |
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Baizhou Zhang
|
5b60b7c651
|
[DSV4] Turn on mhc post pre fusion by default (#35214)
|
2026-08-18 00:03:37 -07:00 |
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|
Andy Ye
|
772018fe36
|
[diffusion] Per-section LoRA adapters on fused linear layers (#34933)
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2026-08-17 23:40:45 -07:00 |
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ashwini rathi
|
5eb117f6ca
|
[XPU] Fix decode graph runner is_current_stream_capturing on non-CUDA devices (#35050)
|
2026-08-18 14:28:13 +08:00 |
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Alexandrandronnie_zheng
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61600c9f39
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[Diffusion][Refactor] Refactor and extract complex RoPE implementation to layers/rotary_embedding for MOVA DiT (#31453)
Co-authored-by: ronnie_zheng <zl19940307@163.com>
|
2026-08-18 09:14:35 +03:00 |
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Jiajun Li
|
e6df23f3c2
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refactor: rename chat response token IDs (#35225)
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2026-08-17 23:07:43 -07:00 |
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Shuwen Wang
|
0077f84d37
|
[mem_cache][8/N] refactor: move MambaPoolHost to pool_host.mamba (#31180)
|
2026-08-18 05:22:45 +00:00 |
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|
Colin Z
|
ea27e3ddab
|
[AMD] Fix Quark Shared Experts Fusion Gate after load-time-override Removal (#35200)
|
2026-08-17 22:10:01 -07:00 |
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|
Zhiyao Jiang
|
9401db3f29
|
[AMD] Scope the EAGLE greedy-verify TP broadcast to ROCm only (#35195)
|
2026-08-17 21:38:24 -07:00 |
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|
Ke Bao
|
d528192bf9
|
Skip inkling sheared bias under batch invariance (#35161)
|
2026-08-18 12:22:58 +08:00 |
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|
amd-danli103andThomas Wang
|
d01812d89e
|
[AMD] Optimize KIMI-K3 with Triton MLA decode kernel by tuning the stage-1 geometry for gfx950 (#34580)
Co-authored-by: Thomas Wang <thomawan@amd.com>
|
2026-08-17 21:16:14 -07:00 |
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Khoa PhamandClaude Opus 5
|
f44a130c5e
|
[DCP] Drop the prefill index-selection syncs by taking each rank's rows by stride (#35084)
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
|
2026-08-17 19:55:51 -07:00 |
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|
Siyuan Chen
|
fcdaaf8a5d
|
[Feature] Optimize TP LMHead with All-to-All (#32313)
|
2026-08-17 19:55:27 -07:00 |
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jiayisunxandMa Mingfei
|
d6c837489a
|
[XPU] Enable fused GDN QKV split Triton kernel on XPU (#30144)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
|
2026-08-18 10:42:58 +08:00 |
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|
MickandYiqi Yang
|
d55f1c28e2
|
[diffusion] feat: load quantized H3 text encoder checkpoints (#34986)
Co-authored-by: Yiqi Yang <yangyiqi8787@gmail.com>
|
2026-08-18 09:10:54 +08:00 |
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|
Liangsheng Yin
|
c0b6474b43
|
[Spec] Reduce host-side overhead in ngram draft prep (#35207)
|
2026-08-17 16:40:06 -07:00 |
|
|
Cheng Wan
|
b3c8f0d923
|
config: one control-plane log for the process (#35028)
|
2026-08-17 16:19:00 -07:00 |
|
|
Cheng Wan
|
c70c7d72a8
|
config: the readback and the resolving view say what they are (#35027)
|
2026-08-17 16:18:19 -07:00 |
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|
Cheng Wan
|
cba3c5d5ac
|
config: the per-instance families read the bags (#35026)
|
2026-08-17 16:17:53 -07:00 |
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|
Cheng Wan
|
a97bc8db32
|
config: the DP/EP topology reads come from the parallel bag (#35025)
|
2026-08-17 16:17:26 -07:00 |
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|
Cheng Wan
|
d2bc697396
|
spec: size the speculative buffers from the bags, not the startup record (#35024)
|
2026-08-17 16:16:56 -07:00 |
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