 cctry
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7a6191c4b9
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Preallocate HiCache MHA staging before post-capture KV sizing (#40256)
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2026-09-21 10:44:29 -07:00 |
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cctry
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7ad55e4386
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[HiCache] TMA-staged host<->device KV transfer kernel (sm_90+) (#40278)
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2026-09-21 10:38:23 -07:00 |
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Eric.Chin.AMDandThomas Wang
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3c71bb018a
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[AMD] Enable GLM DSA prefill top-k to the v2 kernel (#37889)
Co-authored-by: Thomas Wang <thomawan@amd.com>
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2026-09-21 10:31:07 -07:00 |
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5a6a1bb883
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[mxfp8-kv] Skip writes to the reserved CUDA-graph padding slot (#35351)
Co-authored-by: Claude Opus 4.8 <noreply@anthropic.com>
Co-authored-by: Ke Bao <ispobaoke@gmail.com>
Co-authored-by: Sam Shleifer <sam@thinkingmachines.ai>
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2026-09-22 01:21:25 +08:00 |
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Liangsheng Yin
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800613a74b
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[Test] Split the serving perf tests by topic into basic_perf/ and route their thresholds through a kit (#40505)
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2026-09-21 10:05:57 -07:00 |
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Sage
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14e9c40a72
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[Observability] Expose python/rust frontend identity in /server_info (#39993)
Signed-off-by: Sage Ahrac <sagiahrak@gmail.com>
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2026-09-21 23:32:52 +08:00 |
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b63f8416b3
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[Feature] Gigachat 3.5 support (#29189)
Co-authored-by: Stanislav Petrov <stapetrov@sberbank.ru>
Co-authored-by: Viacheslav Barinov <vvadbarinov@sberbank.ru>
Co-authored-by: Viacheslav <viacheslav.teh@gmail.com>
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
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2026-09-21 14:37:55 +08:00 |
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kpjeeja
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b54d5b7c7b
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disaggregation: Fix FakeKVSender queue accumulation (#28652)
Signed-off-by: KP, Jeeja <jeeja.kp@intel.com>
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2026-09-21 14:27:05 +08:00 |
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skyler-apdx
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f5f3c38aad
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[Fix] Preserve YaRN scaling when extending rotary caches (#38786)
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2026-09-21 14:14:05 +08:00 |
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AMRUTHA MandMa Mingfei
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d20cd9d77f
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[XPU]Enable HiSparse hierarchical sparse KV cache on Intel XPU (#32792)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
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2026-09-21 14:07:49 +08:00 |
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jianzhao-xu
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62ba964848
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Fix: post-load staging regression breaks offload meta/sharded_gpu modes (#38779)
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2026-09-21 11:19:07 +08:00 |
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Xueshen Liu
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ab03a8e7eb
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[Perf] Fork-safe import: no CUDA context at import time, lighter argument parsing (#40201)
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2026-09-21 10:48:35 +08:00 |
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zhaozx-cn
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176dbcb85d
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[npu]add chunk gdn kernel and unify ssm state layout for ascend gdn backend (#36187)
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2026-09-21 09:51:19 +08:00 |
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Liangsheng Yin
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76a9065bef
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[Fix] Raise on undelivered embeddings in send_with_url, fix broken tests (#40502)
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2026-09-20 17:35:27 -07:00 |
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Liangsheng Yin
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acd20a516e
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[CI] Give the kernel lane a 5090 suite and move kernel-only tests off the general lane (#40496)
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2026-09-20 16:46:53 -07:00 |
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42875bcd2a
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fix(modelopt): dispatch NVFP4 MoE on the cached backend, not the live global (#38932)
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Co-authored-by: Po-Han Huang (NVIDIA) <53919306+nvpohanh@users.noreply.github.com>
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2026-09-20 19:28:54 -04:00 |
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Mohammad Miadh Angkadandmmangkad
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2fa6b94e34
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[Perf] Fuse the glm5_next mHC attn->MLP boundary (#39200)
Co-authored-by: mmangkad <mohammad.angkad@radixark.ai>
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2026-09-20 16:20:37 -07:00 |
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f31a7bd45c
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Use pinned memory for asynchronous sampling metadata transfers (#39777)
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
Co-authored-by: hnyls2002 <lsyincs@gmail.com>
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2026-09-20 15:31:31 -07:00 |
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Harmya Bhatt
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95521da18d
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[DeepSeek-V4.1] Bound dense prefill indexer memory (#40217)
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2026-09-20 14:43:19 -07:00 |
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Liangsheng Yin
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f6483e479f
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[Test] Drop cause-less disabled tests, fix XPU lane, demote quality gates off base-c (#40288)
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2026-09-20 14:36:02 -07:00 |
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d229952e25
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[Fix] Preserve model runner contracts in prefill CUDA graphs (#35452)
Co-authored-by: Oasis-Git <ayw.sirius19@gmail.com>
Co-authored-by: Ke Bao <ispobaoke@gmail.com>
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2026-09-20 13:53:14 -07:00 |
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Khoa Pham
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b3e4d198af
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[PD] Bound cached-prefix DCP transfers by pack capacity (#40376)
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2026-09-21 01:17:15 +08:00 |
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Jimmy ShongandYangmin Li
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e97614d10c
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[Qwen4-Exp] Build the offloaded PLE table on the meta device so --ple-offload-embedding never materialises it on the accelerator (#39928)
Co-authored-by: Yangmin Li <yangminl@nvidia.com>
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2026-09-20 08:28:25 -07:00 |
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ZY Y
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5f017ffabb
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Update test cases and performance testing framework (#40392)
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2026-09-20 22:42:00 +08:00 |
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Mohammad Miadh AngkadandMohammad Angkad
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8923f4d779
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[Test] Fix optimistic prefill disaggregation test after mamba radix cache removal (#40469)
Co-authored-by: Mohammad Angkad <mohammad.angkad@radixark.ai>
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2026-09-20 22:39:34 +08:00 |
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Liangsheng Yin
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0024efa0de
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[CI] Derive registered-test kind from the registry call instead of the path (#40294)
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2026-09-20 02:01:22 -07:00 |
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HuangJi
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2a0cb2f04e
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[Diffusion][MiniMax-H3] Add SM120 Sage compute for SubBlock sparse attention (#40116)
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2026-09-20 16:40:28 +08:00 |
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Liangsheng Yin
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dc002c85fc
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[Test] Fix OOT DFlash hook test resolving the draft config over the network (#40427)
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2026-09-20 01:25:34 -07:00 |
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Shuwen WangandSeokhoon Kang
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9f3d275940
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[HiCache] Fix sparse hybrid transfer layer IDs (#37870)
Co-authored-by: Seokhoon Kang <sh.kang@postech.ac.kr>
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2026-09-20 16:24:24 +08:00 |
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amd-danli103andHAI
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e54009240a
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[AMD][DSV4] feat: enable DSpark with fp8 unified_kv on gfx950 (#38901)
Co-authored-by: HAI <hixiao@gmail.com>
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2026-09-20 01:16:39 -07:00 |
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Ke Bao
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a8a4d86be9
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Remove swa and mamba radix cache (#40313)
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2026-09-20 16:16:27 +08:00 |
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Qiaolin Yu
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f4c256354c
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[kimi k3][pd disagg] support pp prefill + dcp decode with dspark (#40045)
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2026-09-20 00:15:28 -07:00 |
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Mohammad Miadh AngkadandMohammad Angkad
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22f02cc339
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[Test] Fix scheduler fixtures after prefill burst counting (#40411)
Co-authored-by: Mohammad Angkad <mohammad.angkad@radixark.ai>
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2026-09-20 00:08:04 -07:00 |
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99a44c88d4
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Add out-of-tree DFlash extension points (#38740)
Co-authored-by: Yuhan Chen <yuhanc@fb.com>
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
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2026-09-20 14:54:46 +08:00 |
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Yuxuan ZhangandXinyuan Tong
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9f21fbc34b
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[GLM-5.3-Flash] Reduce KPool planning synchronization and overlap indexer preparation (#39695)
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
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2026-09-19 23:51:17 -07:00 |
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Yuxuan ZhangandXinyuan Tong
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c8eb54c41d
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Fuse GLM-5.3-Flash KDA projections and prefill metadata (#39688)
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
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2026-09-19 23:46:33 -07:00 |
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chaijiacheng888
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2d216a11f8
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[Model] Serve DeepSeek-OCR-2 with its official 768px local-crop geometry (#38996)
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2026-09-20 14:17:21 +08:00 |
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Sasha Sidorov
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59dd2fc734
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[2/N] [Kernel] Fuse padding-preserving HiSparse slot translation (#39837)
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2026-09-20 12:04:03 +08:00 |
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Mohammad Miadh AngkadandMohammad Angkad
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df0dc44931
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[Fix] Forward SWA prealloc reclaim through the DSV4 HiSparse allocator (#40354)
Co-authored-by: Mohammad Angkad <mohammad.angkad@radixark.ai>
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2026-09-19 20:27:51 -07:00 |
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huangtingweiandChao Shi
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020703923d
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[PP + HiCache] Add PP Prefetch Tickets for eager cross-stage storage prefetch (#36700)
Co-authored-by: Chao Shi <stepinto@live.com>
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2026-09-20 11:19:31 +08:00 |
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Tri Dao
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d82d653f96
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Enable optimistic prefill for Mamba radix-cache models (#40184)
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2026-09-19 19:28:11 -07:00 |
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huangtingweiandZhangheng
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e9300f643e
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[Unified Cache][9/N] add opt-in MLA load deduplication for Mooncake Linker (#39565)
Co-authored-by: Zhangheng <hzh0425@apache.org>
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2026-09-20 09:56:56 +08:00 |
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AndyLi429andAndyLi429
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d903351a66
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[NPU][bugfix] update low latency quantization input and update MXFP8 tests (#38831)
Co-authored-by: AndyLi429 <AndyLi429@noreply.gitcode.com>
|
2026-09-20 09:55:30 +08:00 |
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f9c2791460
|
[diffusion] model: support qwen-image-2.1 (#39983)
Co-authored-by: Mick Qian <mickqian@users.noreply.github.com>
Co-authored-by: BBuf <1182563586@qq.com>
|
2026-09-20 09:46:09 +08:00 |
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BourneSun0527andEven Zhou
|
d2f291c934
|
[NPU][DSV4]dsv4 enable cpp (#39820)
Co-authored-by: Even Zhou <even.y.zhou@outlook.com>
|
2026-09-20 09:17:27 +08:00 |
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YAMY
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9cc7da2ab0
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[MegaMoE] Wire Qwen MoE blocks to DeepGEMM MegaMoE (MXFP4 and NVFP4 experts) (#38080)
|
2026-09-19 16:00:38 -07:00 |
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3a64faa1f2
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Fix disagg PP MTP for GLM-5.2 (#39378)
Co-authored-by: Julien Lin <jullin@nvidia.com>
Co-authored-by: YAMY1234 <74099316+YAMY1234@users.noreply.github.com>
Co-authored-by: Yangmin Li <yangminl@nvidia.com>
|
2026-09-19 13:55:07 -07:00 |
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Zhiqiang Xie
|
7a6c652c77
|
[HiCache] Auto-size the host pool to fit available host memory (#40135)
|
2026-09-19 12:50:43 -07:00 |
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metamergebotandcctry
|
9e5a62a767
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[Logprob] Serve input-logprob temporaries from CUDA-graph-pool dead space (#40038)
Co-authored-by: cctry <csycfl@gmail.com>
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2026-09-19 12:03:52 -07:00 |
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7b67a96640
|
[DSV4] Chunk the indexer MQA logits by query rows under a free-memory budget (#39095)
Signed-off-by: Shiki Wu <shikiw@nvidia.com>
Co-authored-by: Baizhou Zhang <sobereddiezhang@gmail.com>
Co-authored-by: Yuwei An <ayw.sirius19@gmail.com>
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2026-09-19 11:53:20 -07:00 |
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