 Ma Mingfei
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41e0b4b369
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[CPU] add fused input proj for qwen3.5 (#31171)
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2026-07-15 15:06:24 +08:00 |
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Yuan Luoandluoyuan.luo
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a649b5a9db
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[KDA] Add FlashInfer SM100 KDA decode + MTP (target_verify) backend (#30113)
Co-authored-by: luoyuan.luo <luoyuan.luo@antgroup.com>
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2026-07-15 15:04:20 +08:00 |
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fzyzcjy
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1afab30577
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Fix bookkeeping fields not encapsulated with real allocations in normal alloc, PD pre-alloc, DFlash and EAGLE (#29432)
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2026-07-15 14:52:21 +08:00 |
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fzyzcjy
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e789ca24a7
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Lightweight extract allocation logic from mem_cache/common.py to more clearly show nearly parallel variants (#29431)
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2026-07-15 14:49:37 +08:00 |
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fzyzcjy
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c315df49bb
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Fix abusing presence of req.req_pool_idx to indicate the presence of req.kv resources (#29430)
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2026-07-15 14:48:39 +08:00 |
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fzyzcjy
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2d979f1d8c
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Let the presence of req.kv indicate the existence of owned kv resources (#29429)
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2026-07-15 14:47:16 +08:00 |
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fzyzcjy
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27256aee5b
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Let cache backend do not couple with owned committed kv details and avoid kv_committed_freed/kv_overallocated_freed fields (#29428)
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2026-07-15 14:43:10 +08:00 |
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fzyzcjy
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d8d76c4d12
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Introduce req.kv container for coupled owned kv field lifecycle (#29427)
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2026-07-15 14:40:38 +08:00 |
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fzyzcjy
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201ddeaba1
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Avoid relaying per-step outputs through ScheduleBatch fields in disagg prefill and PP (#30677)
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2026-07-15 14:33:37 +08:00 |
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fzyzcjy
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01343d2759
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Avoid implicit running_batch access in dllm and pdmux scheduling (#30676)
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2026-07-15 14:33:00 +08:00 |
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fzyzcjy
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21c62b9830
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Rewrite pause_generation retract path as req-level release and requeue for clarity (#30675)
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2026-07-15 14:32:12 +08:00 |
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fzyzcjy
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1967b9ec99
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Fix missed hisparse release and stale field cleanup in pause retract (#30674)
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2026-07-15 14:31:11 +08:00 |
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fzyzcjy
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b6cc897fea
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Fix non-existent abort mode in Scheduler.pause_generation and inline retract_all (#30673)
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2026-07-15 14:27:48 +08:00 |
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fzyzcjy
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52a88fb212
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Avoid mutating ScheduleBatch fields in place (#30672)
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2026-07-15 14:27:08 +08:00 |
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fzyzcjy
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e77d95c3d5
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Pass per-forward overrides to ForwardBatch.init_new as explicit arguments (#30670)
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2026-07-15 14:25:59 +08:00 |
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fzyzcjy
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861d97d24d
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Remove dead ScheduleBatch fields and avoid inplace seq_lens bump (#30669)
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2026-07-15 14:23:31 +08:00 |
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AMD-yanfeiwang
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a3194d3585
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[AMD] Remove ROCm page_first+kernel -> layer_first HiCache fallback (follow-up to #28534) (#30622)
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2026-07-14 22:48:16 -07:00 |
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Xiaoyu ZhangandClaude Fable 5
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4aadf94146
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[Kernel] Relocate vendored fla and mamba kernel trees to sglang.kernels (RFC #29630, Phase 2.5, 7/7) (#30795)
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
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2026-07-15 12:52:15 +08:00 |
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ANSHUMAN TRIPATHY
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23f2b77d82
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Make UTs compatible for XPU (#27106)
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2026-07-15 12:35:56 +08:00 |
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Xiaoyu ZhangandClaude Fable 5
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c00131ebaa
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[Kernel] Migrate linear-attention, MiniMax-sparse and diffusion kernels to sglang.kernels (RFC #29630, Phase 2.5, 6/7) (#30793)
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
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2026-07-15 11:21:36 +08:00 |
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Xiaoyu ZhangandClaude Fable 5
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ba5be86d42
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[Kernel] Migrate DSA + DSV4 attention kernels to sglang.kernels (RFC #29630, Phase 2.5, 5/7) (#30792)
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
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2026-07-15 11:11:22 +08:00 |
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4ae9cc3c81
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Fix gate stride for 4D decode layouts (#31231)
Co-authored-by: lmzheng <lmzheng@fb.com>
Co-authored-by: michael604work <michael604@meta.com>
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2026-07-14 20:06:50 -07:00 |
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Lianmin Zheng
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b4fdce3b63
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Fix post-capture KV sizing for SWA pools (#31092)
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2026-07-14 20:06:15 -07:00 |
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Polisetty V R K Jyothendra Varma
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532cd337ed
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[Intel GPU] DeepSeek V4 12/N: use sgl-kernel implementation of silu_and_mul_clamp to run on XPU (#28428)
Signed-off-by: P V R K Jyothendra Varma <polisetty.v.r.k.jyothendra.varma@intel.com>
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2026-07-15 11:03:53 +08:00 |
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Polisetty V R K Jyothendra VarmaandMa Mingfei
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46b675ce70
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[Intel GPU] DeepSeek V4 11/N: support fp8_paged_mqa_logits_triton from sgl-kernel to run on XPU (#28059)
Signed-off-by: P V R K Jyothendra Varma <polisettyvarma@gmail.com>
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
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2026-07-15 11:03:35 +08:00 |
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Mick
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43124cdd90
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fix: fix image benchmark backend parity (#30867)
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2026-07-15 10:11:22 +08:00 |
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Liangsheng Yin
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76dc427806
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[Spec] Single-source num_tokens_per_req derivation and access (#31013)
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2026-07-14 18:41:08 -07:00 |
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Liangsheng Yin
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ca0ee3f1a8
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[Spec] Consolidate spec-worker weight updates into BaseSpecWorker via draft_runners (#31078)
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2026-07-14 18:39:46 -07:00 |
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weireweireandweireweire
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a9cf5e68e6
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[DSV4] Remove per-step seqlen D2H from speculative to make overlap scheduler work (#30365)
Co-authored-by: weireweire <20922698+weireweire@users.noreply.github.com>
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2026-07-14 18:01:22 -07:00 |
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WenhaoZhang
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90f10cbe26
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[diffusion] post_training: Add LoRA IPC weight sync via lora_merge mode (#31029)
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2026-07-15 08:42:54 +08:00 |
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Liangsheng Yin
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50d1edaa7f
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[misc] Move SchedulerRecvSkipper into scheduler_components (#31222)
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2026-07-14 16:35:04 -07:00 |
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paulzhang-tm
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463a3f4248
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[Mamba] Support configurable conv-window layouts (#31059)
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2026-07-14 14:41:10 -07:00 |
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paulzhang-tm
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08c46e1f1a
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Add dummy forward batch preparation hook (#31070)
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2026-07-14 14:30:31 -07:00 |
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0d89564d27
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Support scheduler_recv_interval (recv skipper) under DP-attention (#30457)
Co-authored-by: Cursor <cursoragent@cursor.com>
Co-authored-by: hnyls2002 <lsyincs@gmail.com>
Co-authored-by: Liangsheng Yin <hnyls2002@gmail.com>
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2026-07-14 14:02:58 -07:00 |
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cctryandcctry
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cb47a68717
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[PD] Stride KV token->page indices on device before D2H copy (#31173)
Co-authored-by: cctry <cctry@fb.com>
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2026-07-14 10:08:30 -07:00 |
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hunhokimandHun-ho Kim
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a5c3e0283f
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[Bug fix] Account for KV replication fan-out in transfer-byte metrics (#30351)
Co-authored-by: Hun-ho Kim <hunho.kim@samsung.com>
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2026-07-14 10:08:24 -07:00 |
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Mick
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04af94d150
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fix: avoid tilelang cuda runtime pollution (#30870)
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2026-07-14 22:30:27 +08:00 |
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Peng Xingchen
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f853293440
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[NPU] Fix CPU device for node topology probe (#30619)
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2026-07-14 22:17:54 +08:00 |
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Ma Mingfei
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31548781e0
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[CPU] bypass scoring_func argument in topk for cpu device (#31110)
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2026-07-14 21:48:22 +08:00 |
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Kevin FlansburgandShangming Cai
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bbb5702a3c
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fix: avoid double KV release on disaggregated prefill grammar errors (#30937)
Co-authored-by: Shangming Cai <csmthu@gmail.com>
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2026-07-14 20:16:58 +08:00 |
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Mick
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43241b7f3f
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[diffusion] model: support fal Ideogram V4 Fast and Instant (#31177)
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2026-07-14 19:51:35 +08:00 |
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Xiaoyu ZhangandClaude Fable 5
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ee000f6734
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[CI] Fix SGLANG_JIT_KERNEL_RUN_FULL_TESTS never activating the nightly full jit-kernel sweep (#31042)
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
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2026-07-14 17:32:29 +08:00 |
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Xiaoyu ZhangandClaude Fable 5
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1a35440c4a
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[Kernel] Migrate generic attention kernels to sglang.kernels (RFC #29630, Phase 2.5, 4/7) (#30789)
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
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2026-07-14 16:53:46 +08:00 |
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fzyzcjy
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0fe2dbd42c
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Split initialize() into orchestration helpers (#31169)
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2026-07-14 16:09:00 +08:00 |
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Ankith Averineni
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64a70c9097
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[AMD] jit_kernel: complete utils.cuh HIP-compat (cudaDevAttr / cudaDeviceGetAttribute) (#31143)
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2026-07-14 16:06:36 +08:00 |
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fzyzcjy
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bf04cc9b14
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Extract cuda-graph setup into a module (#31168)
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2026-07-14 16:04:45 +08:00 |
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fzyzcjy
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ed2fcd3201
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Extract attention-backend setup into a module (#31167)
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2026-07-14 16:03:48 +08:00 |
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fzyzcjy
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54f99a21d5
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Narrow component dependencies to injected fields instead of ModelRunner (#31166)
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2026-07-14 16:03:07 +08:00 |
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fzyzcjy
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6999007a13
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Drop ModelRunner's duplicated parallel-degree fields and read them via self.ps (#31165)
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2026-07-14 16:02:40 +08:00 |
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fzyzcjy
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cfd17301a8
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Extract per-architecture KV-cache pool builders into KVCacheConfigurator (#31163)
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2026-07-14 16:02:09 +08:00 |
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