Liangsheng Yin
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3ffe72517f
|
[Spec] Remove the dead spec V1 scheduler paths (#27977)
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2026-06-11 18:31:13 -07:00 |
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Cheng Wan
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2e74ff192c
|
[DSV4] Use int64 for compressor out_loc tensors (#27973)
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2026-06-11 17:45:34 -07:00 |
|
Cheng Wan
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97a0031799
|
[lint] Enable Ruff UP037 to drop redundant quoted annotations (#27984)
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2026-06-11 17:38:05 -07:00 |
|
Liangsheng Yin
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c0480a88be
|
[Spec] Retire Spec V1 (#27964)
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2026-06-11 16:15:15 -07:00 |
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Oguz Ulgen
|
949326d922
|
Add SGLANG_ENABLE_WAR_BARRIER to force-enable the overlap scheduler WAR barrier on non-CUDA (e.g. AMD) (#27967)
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2026-06-11 15:38:37 -07:00 |
|
 
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d71e9bede6
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[bugfix] commit Mamba states after NGRAM target verify (#26351)
Co-authored-by: xbfs <xuebf1@lenovo.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
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2026-06-11 15:11:18 -07:00 |
|
Yueming Yuan
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cd075d1f64
|
[RL] convert DeepSeek V4 APE layout through weight loader (#27307)
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2026-06-11 15:05:27 -07:00 |
|
Liangsheng Yin
|
fee717f303
|
[Spec] Fold the DFLASH worker base into DFlashWorkerV2 on BaseSpecWorker (#27950)
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2026-06-11 14:54:28 -07:00 |
|
Liangsheng Yin
|
acdb39edd2
|
[Spec] Remove the DFLASH V1 worker path (#27959)
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2026-06-11 14:37:58 -07:00 |
|
Wang, FangYuan
|
6e885c844f
|
Revert "[AMD] Fix DeepSeek V4 Pro c128 state tensor dtype mismatch error and c4_sparse_raw_indices attribute error in cuda graph phase" (#27919)
|
2026-06-11 14:25:32 -07:00 |
|
Liangsheng Yin
|
df5055e00f
|
Bump spec logprob match delta for the bf16 eagle fixture (#27952)
|
2026-06-11 14:21:07 -07:00 |
|
  ![github-actions[bot]](/assets/img/avatar_default.png)
|
ec0eb6cce8
|
Support MiMo v2 ASR (#26278)
Co-authored-by: github-actions[bot] <github-actions[bot]@users.noreply.github.com>
Co-authored-by: yanyihan <yanyihan@xiaomi.com>
Co-authored-by: zhuqingchao <zhuqingchao@xiaomi.com>
|
2026-06-11 13:43:13 -07:00 |
|
Jackey Hua
|
24c5d76f74
|
fix: per-sequence last-token embedding in EAGLE3/MTP draft for batched multimodal spec decoding (#27846)
|
2026-06-11 13:33:16 -07:00 |
|
 cctryandcctry
|
10219bd9d6
|
[PD] Fix negative prefill kv_transfer_alloc_ms under optimistic prefill (#27885)
Co-authored-by: cctry <cctry@fb.com>
|
2026-06-11 13:12:25 -07:00 |
|
Yuwei An
|
880e6f66fc
|
[BCG] Share output buffers across capture sizes + typed ShapeKey (#27857)
|
2026-06-11 11:58:05 -07:00 |
|
Brian Chao
|
7f57b344c9
|
[diffusion] feat: progressive resolution growing for Ideogram 4 via GPU DCT upsampling with up to 1.56× speedup (#27736)
|
2026-06-11 23:16:53 +08:00 |
|
 Chi McIsaacandMick
|
b2728bda9d
|
[diffusion] feat: use fused w8a8 kernel for Ideogram4 weight-only linear as an opt-in (#27590)
Co-authored-by: Mick <mickjagger19@icloud.com>
|
2026-06-11 23:15:27 +08:00 |
|
 Xiaoyu ZhangandBBuf
|
06e0df5899
|
Optimize Qwen3 Next FP8 MoE on H200 (#26204)
Co-authored-by: BBuf <xiaoyu.zhang@radixark.net>
|
2026-06-11 22:18:43 +08:00 |
|
 Xiaoyu ZhangandBBuf
|
1a6b5561db
|
Fix MLA scaling when YARN scaling is disabled (#26203)
Co-authored-by: BBuf <xiaoyu.zhang@radixark.net>
|
2026-06-11 22:17:55 +08:00 |
|
Xiaoyu Zhang
|
d571e076fa
|
[codex] Centralize more inline Triton kernels (#27429)
|
2026-06-11 22:17:26 +08:00 |
|
Mick
|
d9110d971e
|
[diffusion] fix: fix wan ti2v sp timestep padding (#27876)
|
2026-06-11 22:13:25 +08:00 |
|
ybyang
|
8077fb1df7
|
fix(deepgemm): align PP-parallel warmup bs to CP padding (#27922)
|
2026-06-11 20:52:45 +08:00 |
|
Mick
|
9e9fde1478
|
[diffusion] Revert "Mistral3 add tensor parallel support for diffusion text encoder " (#27892)
|
2026-06-11 20:33:45 +08:00 |
|
 Shangming CaiandAbatom
|
6a012fbb2d
|
[PD] Fix ZMQ stale socket reconnection in PD disaggregation (#27796)
Signed-off-by: Shangming Cai <csmthu@gmail.com>
Co-authored-by: Abatom <abzhonghua@gmail.com>
|
2026-06-11 19:51:12 +08:00 |
|
 shuwennandClaude Opus 4.8
|
66076f2409
|
[mem_cache][3/N] refactor: move HiSparse allocators to allocator/hisparse.py (#26678)
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
|
2026-06-11 19:50:24 +08:00 |
|
Zhonghua Deng
|
be45745f38
|
[EPD] fix: zmq PUSH socket reconnect-aware connection management with tcp keepalive (#27039)
|
2026-06-11 19:32:31 +08:00 |
|
Mohammad Miadh Angkad
|
7e245afefe
|
[CI] Fix registered sigmoid gate mul test location (#27909)
|
2026-06-11 18:52:37 +08:00 |
|
Mohammad Miadh Angkad
|
6ac9f66596
|
Remove MoE prefill CUDA graph disable guard (#27841)
|
2026-06-11 18:30:15 +08:00 |
|
luoroger37
|
54cba63b6c
|
Fix paged SWA free mapping cleanup (#27779)
|
2026-06-11 18:25:24 +08:00 |
|
jacky.cheng
|
22c7285a26
|
[AMD] Fuse sigmoid + mul attention output gate into single Triton kernel (#27630)
|
2026-06-11 02:05:05 -07:00 |
|
jacky.cheng
|
f4b3b99413
|
[AMD] Enable fused GDN QKV split Triton kernel on HIP (#27583)
|
2026-06-11 02:01:27 -07:00 |
|
Liangsheng Yin
|
493bb6ae0d
|
Fix fp16 NaN flake in spec CI: bf16 eagle fixture; sanitize NaN logits in sampler (#27883)
|
2026-06-11 01:16:12 -07:00 |
|
 kkandwunhuang
|
b8376aebd0
|
[AMD] Fix the dsv4 performance of MoE issue. (#27858)
Co-authored-by: wunhuang <wunhuang@amd.com>
|
2026-06-11 01:06:54 -07:00 |
|
gaopengff
|
dc1e46ec8f
|
[Intel GPU]Add sycl mrope pass for xpu device (#27646)
|
2026-06-11 12:25:55 +08:00 |
|
Zhangheng
|
5e0271536a
|
[UnifiedTree]: HybridModel launches HiCache via UnifiedTree by default. (#27759)
|
2026-06-11 12:03:36 +08:00 |
|
Zilin Zhu
|
9788c8e867
|
[RL] Handle Mooncake buffers across memory release (#27696)
|
2026-06-11 11:15:00 +08:00 |
|
YAMY
|
f8b0a120b8
|
fix: DSV4 BCG compress-prefill plan OOB on underfilled (tiny) prefill replay (#27747)
|
2026-06-10 20:02:24 -07:00 |
|
Cheng Wan
|
f4f30d7d23
|
[Fix] Use int64 seq_lens across all CUDA graph runners and backends (#27840)
|
2026-06-10 19:54:58 -07:00 |
|
Yihao Wang
|
b4bed8c398
|
[diffusion] fix: cast to float32 (from float64) in triton kernel to unblock torch.compile (#27709)
|
2026-06-11 10:29:21 +08:00 |
|
David Wang
|
588d1f7bc9
|
[Feature] Spec V2 DFlash Support (#23000)
|
2026-06-10 19:27:42 -07:00 |
|
Hexq0210
|
475e9d25bf
|
bugfix for npu mtp graph runner (#27808)
|
2026-06-11 10:09:50 +08:00 |
|
YanbingJiang
|
66989a7642
|
Fix gpt-oss-20b with mxfp4 support for Xeon (#27782)
|
2026-06-11 09:16:16 +08:00 |
|
fxmarty-amd
|
99ab90c5b7
|
[AMD] Restore AMD piecewise CUDA graph support dropped by #23906 (#27811)
|
2026-06-10 17:43:48 -07:00 |
|
 Lijuan TangandClaude Opus 4.8
|
5f913c1135
|
[Fix] Emulate PDEATHSIG on macOS to prevent orphaned worker processes (#27190)
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
|
2026-06-10 17:43:27 -07:00 |
|
 Yongji Wuandhzh0425
|
db061e97c0
|
[Unified] Fix UnifiedRadixCache write_backup issue in write-back mode(#27108)
Co-authored-by: hzh0425 <hzh0425@apache.org>
|
2026-06-11 08:28:24 +08:00 |
|
 
|
740305e1d9
|
[HiCache] Add opt-in LRU eviction to file storage backend (CP-aware) (#26670)
Co-authored-by: Zhangheng <hzh0425@apache.org>
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
|
2026-06-11 08:21:59 +08:00 |
|
Liangsheng Yin
|
16124fc9b2
|
[Metrics] Fix fwd_occupancy reading NaN on every decode log line; probe-free base-a (#27836)
|
2026-06-10 15:42:19 -07:00 |
|
Mohammad Miadh Angkad
|
bdf3ef6421
|
[CI] Fix registered QK Gemma RMSNorm test location (#27839)
|
2026-06-10 15:21:59 -07:00 |
|
jacky.cheng
|
0da18f8d91
|
[AMD][Perf] Fuse QK RMSNorm + gate extraction Triton kernel for Qwen3.5 on HIP (#27656)
|
2026-06-10 14:29:33 -07:00 |
|
Baizhou Zhang
|
3c1b0fb226
|
[1/n] [CP] Simplify prefill context parallel server args (#27312)
|
2026-06-10 14:11:38 -07:00 |
|