Kaixi
10bb2eff3d
[BCG] Restore Qwen3.5 MRoPE fusion under breakable CUDA graph ( #27918 )
2026-07-09 14:30:05 -07:00
DarkSharpness and Claude Fable 5
bda1dc0d95
[DSA] Fix top-k v2 emitting invalid indices under tie overflow / inf scores (IMA in FA3 sparse decode) ( #30645 )
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Co-authored-by: Claude Fable 5 <noreply@anthropic.com >
2026-07-09 14:28:21 -07:00
Thomas Wang and HAI
8d0fd34150
[AMD] Enable unified-KV HiCache on DeepSeek-V4 ( #29417 )
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Co-authored-by: HAI <hixiao@gmail.com >
2026-07-09 12:58:47 -07:00
Xinyuan Tong
7132af28de
Fix garbage output for bare-tekken Mistral checkpoints (e.g. Leanstral) ( #30396 )
2026-07-10 00:08:38 +05:30
ICENacl and chunjiang.hc
b717546fab
fix(mtp): avoid mtp perf regression in deepseek when enable eplb ( #28982 )
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Co-authored-by: chunjiang.hc <chunjiang.hc@alibaba-inc.com >
2026-07-09 11:29:07 -07:00
amd-danli103 and amd-danli103
462b6171bd
[AMD] Fix stale SWA ring buffer on radix prefix reuse for DeepSeek-V4 with unified_kv backend ( #30339 )
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Co-authored-by: amd-danli103 <dan2.li@amd.com >
2026-07-09 11:28:22 -07:00
Mohammad Miadh Angkad
b0ecbceed9
[Bugfix] Migrate retired parallel accessors ( #30653 )
2026-07-09 11:22:34 -07:00
26ba3458d3
[AMD] Fix int32 offset overflow in Triton decode-attention kernels ( #28788 )
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Co-authored-by: Chun Fang <chun.fang@amd.com >
Co-authored-by: HaiShaw <hixiao@gmail.com >
2026-07-09 11:20:04 -07:00
YAMY
2e4d6368c3
[GDN] Auto-select FlashInfer GDN prefill on validated SM100 configs ( #29734 )
2026-07-10 00:26:00 +08:00
cctry and cctry
1959335997
refactor(load-snapshot): build LoadSnapshot directly, drop legacy get_loads IPC ( #30525 )
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Co-authored-by: cctry <cctry@fb.com >
2026-07-09 05:58:10 -07:00
7aab39a18b
[Diffusion] SGLang backend for GLM Image AR. Step 1 - Separate server ( #25381 )
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Co-authored-by: yhyang201 <yhyang201@gmail.com >
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com >
Co-authored-by: yuefeng Wu <33725817+ChefWu551@users.noreply.github.com >
Co-authored-by: wuyuefeng <wuyuefeng@noreply.gitcode.com >
2026-07-09 15:54:50 +03:00
fzyzcjy
6ab7a65d94
Support grad injection and step override in the dumper's model dump ( #30657 )
2026-07-09 20:26:05 +08:00
fzyzcjy
5b28465eb9
Cap diagnostic detail computation for failing tensors ( #30656 )
2026-07-09 20:19:51 +08:00
fzyzcjy
287291c232
Fix rel_diff being nan for bitwise-identical tensors ( #30655 )
2026-07-09 20:16:18 +08:00
fzyzcjy
0d7e8cfb85
Support per-regex diff-threshold predicates in the tensor comparator ( #30654 )
2026-07-09 20:15:36 +08:00
Shijin Zhang
8e54517f02
[Feat][GLM5.2] Add DSA Cache Layer Split under Prefill CP ( #29421 )
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Signed-off-by: Shijin Zhang <75300765+Dovis01@users.noreply.github.com >
2026-07-09 03:03:56 -07:00
billishyahao and HAI
336b64ecce
[AMD] fix dsv4 indexer dtype dispatch on gfx950 ( #29479 )
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Co-authored-by: HAI <hixiao@gmail.com >
2026-07-09 02:54:00 -07:00
Liangsheng Yin
078f06fbf4
[Refactor] Share chat encoding dispatch between serving and offline tools ( #30623 )
2026-07-09 02:45:42 -07:00
Cheng Wan
1f15308dca
[refactor] Retire the legacy config accessor and the remaining process singletons ( #30493 )
2026-07-09 02:10:47 -07:00
Chengze Fan
122b3266a2
Add opt-in SGLANG_ROPE_CACHE_FP32 to keep RoPE cache in fp32 on non-CUDA ( #29729 )
2026-07-09 02:10:39 -07:00
Cheng Wan
e703f9e566
[refactor] Adopt get_parallel() everywhere and close out the parallel wrapper surface ( #30492 )
2026-07-09 02:09:39 -07:00
Cheng Wan
06eb1b1838
[refactor] Split the DP gathered-buffer state between flags.dp and ctx.forward ( #30491 )
2026-07-09 02:09:21 -07:00
Cheng Wan
fef2128e19
[refactor] Add the per-forward flags tier: ctx.forward ( #30490 )
2026-07-09 02:09:03 -07:00
Cheng Wan
65b14881c5
[refactor] Move the EP dispatcher and fusion-workspace manager state onto ctx.resources ( #30489 )
2026-07-09 02:08:35 -07:00
Liangsheng Yin
bc5d376c2c
[Bench] Add fixed-prompt mode and per-request spec accept length metrics ( #30615 )
2026-07-09 02:06:04 -07:00
Zhiyao Jiang and Xinyu Jiang
bd7e54d737
[AMD] Fix AITER custom all-gather CUDA-graph capture crash under torch_memory_saver ( #30557 )
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Co-authored-by: Xinyu Jiang <xinyuj2@andrew.cmu.edu >
2026-07-09 01:30:51 -07:00
AMD-yanfeiwang and Duyi-Wang
d74619b373
[AMD] Enable JIT staged HiCache write-back and fix CPU-index crash ( #28534 )
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Co-authored-by: Duyi-Wang <duyi.wang@amd.com >
2026-07-09 01:22:37 -07:00
Liangsheng Yin
61602b95fb
[Fix] Prevent silent VLM server crash when /dev/shm is exhausted during multimodal feature transport ( #30602 )
2026-07-09 00:44:42 -07:00
Ata Fatahi
866ae6848f
[PDD] Add true request retraction for PDD ( #25372 )
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Signed-off-by: Ata Fatahi <immrata@gmail.com >
2026-07-09 15:33:01 +08:00
Mohammad Miadh Angkad
666a09fe2a
Disable multi-threaded load by default when prefetch is on ( #30146 )
2026-07-09 00:28:53 -07:00
Liangsheng Yin
64e2a73c80
[Fix] Serialize FanOutCommunicator queueing calls with a FIFO-fair asyncio.Lock ( #30606 )
2026-07-09 00:04:43 -07:00
Yuwei An and Claude Fable 5
0562ccb1a8
Move breakable CUDA graph back into model_executor/runner_backend_utils ( #30586 )
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Co-authored-by: Claude Fable 5 <noreply@anthropic.com >
2026-07-09 14:19:16 +08:00
weireweire and weireweire
1c9eb6bb0b
[DSV4] Fix draft SWA transfer for disaggregated MTP ( #30461 )
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Co-authored-by: weireweire <20922698+weireweire@users.noreply.github.com >
2026-07-09 13:18:34 +08:00
Haotong Zou and Valentine233
3b43df5b6d
Support speculative decoding on CPU ( #27862 )
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Co-authored-by: Valentine233 <xuan.liao@intel.com >
2026-07-09 10:27:09 +08:00
jianan-gu and Ma Mingfei
177c048c68
[Diffusion][CPU] Adding AMX optimizations for CPU platform ( #28527 )
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Co-authored-by: Ma Mingfei <mingfei.ma@intel.com >
2026-07-09 10:26:22 +08:00
WenhaoZhang
395a2201e4
[diffusion] rl: enable RL rollout path for LTX-2.3 post-training ( #28926 )
2026-07-09 10:24:06 +08:00
6bce72d968
[Intel GPU] xpu_piecewise: fall back to eager when PCG capture stream is unset ( #30235 )
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Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com >
Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com >
2026-07-09 10:21:43 +08:00
Baizhou Zhang
2b3d9ad375
[Tiny] Fix docstring in CP abstractions ( #30579 )
2026-07-08 18:41:40 -07:00
cen121212
0ffed946f2
[NPU] Add extra topk_weights input in deepep ll dispatch ( #29480 )
2026-07-09 09:23:29 +08:00
Xinyuan Tong
074bb928f0
Move template manager files under parser; update CODEOWNERS ( #26052 )
2026-07-08 16:47:36 -07:00
Liangsheng Yin
8f9307736a
[misc] Add CI-only guards for the FutureMap seq_lens relay ( #30471 )
2026-07-08 15:29:53 -07:00
cctry
096551eed6
Make CUDA graph disabling PD-role-aware (prefill/decode) ( #30409 )
2026-07-08 15:08:22 -07:00
07ef650ef7
[AMD] Fix GLM-5.2 MTP Quark excludes ( #30265 )
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Co-authored-by: zhaolin <zhaolin@amd.com >
Co-authored-by: Raiden-Makoto <Raiden-Makoto@users.noreply.github.com >
Co-authored-by: HAI <hixiao@gmail.com >
2026-07-08 14:57:10 -07:00
Lianmin Zheng
ca8f15cd70
Fix FlashInfer A2A IMA by DP-synchronizing the decode graph bucket ( #30242 ) ( #30450 )
2026-07-08 14:34:49 -07:00
Liangsheng Yin
10e7f2925f
[Fix] Chain the seq_lens publish event records so prebuilt seeding keeps the forward fence ( #30435 )
2026-07-08 13:43:09 -07:00
Xinyuan Tong and EazyReal
45019b56ce
[Bugfix] Map reasoning_effort=low to Nemotron-3 Super low_effort + warn on unsupported levels ( #30463 )
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Co-authored-by: EazyReal <8047065+EazyReal@users.noreply.github.com >
2026-07-08 12:19:44 -07:00
sonle5 and sunxxuns
8d2b66fd90
Fix gfx95 bpreshuffle FP8 activation scale layout ( #29275 )
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Co-authored-by: sunxxuns <126995791+sunxxuns@users.noreply.github.com >
2026-07-08 10:55:09 -07:00
Mohammad Miadh Angkad
04e4fadff3
Use FP32 logits in MoEGate fallbacks ( #30323 )
2026-07-08 23:43:45 +08:00
Xiaoyu Zhang
b8ca06fdad
Fix zero expert routed ids for MoE backends ( #30387 )
2026-07-08 21:23:25 +08:00
shuwenn
108a183f6b
[mem_cache][6/N] refactor: move MHA host-pool into pool_host/mha.py ( #30249 )
2026-07-08 20:12:52 +08:00
Kaixi