 Guangda LiuandGuangda Liu
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04c0913434
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[HiSparse] Add MHA hisparse support for MiniMax M3 (#31446)
Co-authored-by: Guangda Liu <bingps@users.noreply.github.com>
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2026-09-22 13:28:03 +08:00 |
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Cheng Wan
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506698761d
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[unified-memory] Hierarchical cache for every unified pool shape (#37507)
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2026-09-21 16:50:37 -07:00 |
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Cheng Wan
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acac4dd9d9
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[Refactor] Clean up parallel runtime comments (#40632)
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2026-09-21 14:32:22 -07:00 |
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Cheng Wan
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73f071db52
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Deprecate the parallel getters the context answers, and ratchet them shut (#40342)
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2026-09-21 12:25:32 -07:00 |
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Cheng Wan
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2d0e94e3a3
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Check the topology identities where the layout is written, and build at the published widths (#40340)
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2026-09-21 12:22:59 -07:00 |
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cctry
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7a6191c4b9
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Preallocate HiCache MHA staging before post-capture KV sizing (#40256)
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2026-09-21 10:44:29 -07:00 |
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Shuwen WangandSeokhoon Kang
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9f3d275940
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[HiCache] Fix sparse hybrid transfer layer IDs (#37870)
Co-authored-by: Seokhoon Kang <sh.kang@postech.ac.kr>
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2026-09-20 16:24:24 +08:00 |
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amd-danli103andHAI
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e54009240a
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[AMD][DSV4] feat: enable DSpark with fp8 unified_kv on gfx950 (#38901)
Co-authored-by: HAI <hixiao@gmail.com>
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2026-09-20 01:16:39 -07:00 |
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Ke Bao
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a8a4d86be9
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Remove swa and mamba radix cache (#40313)
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2026-09-20 16:16:27 +08:00 |
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Sasha Sidorov
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59dd2fc734
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[2/N] [Kernel] Fuse padding-preserving HiSparse slot translation (#39837)
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2026-09-20 12:04:03 +08:00 |
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Mohammad Miadh AngkadandMohammad Angkad
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df0dc44931
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[Fix] Forward SWA prealloc reclaim through the DSV4 HiSparse allocator (#40354)
Co-authored-by: Mohammad Angkad <mohammad.angkad@radixark.ai>
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2026-09-19 20:27:51 -07:00 |
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huangtingweiandChao Shi
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020703923d
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[PP + HiCache] Add PP Prefetch Tickets for eager cross-stage storage prefetch (#36700)
Co-authored-by: Chao Shi <stepinto@live.com>
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2026-09-20 11:19:31 +08:00 |
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Zhiqiang Xie
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7a6c652c77
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[HiCache] Auto-size the host pool to fit available host memory (#40135)
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2026-09-19 12:50:43 -07:00 |
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993d1fccba
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[ROCm] Widen the HiCache JIT copy rounds and enable the K-only host pool (#37152)
Co-authored-by: Xiaobo Chen <xiaobche@smci355-ccs-aus-n05-33.prov.aus.ccs.cpe.ice.amd.com>
Co-authored-by: HAI <hixiao@gmail.com>
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2026-09-19 08:58:10 -07:00 |
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Lianmin Zheng
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5d703de9e4
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[HiCache] Size MHA host pools from device row width (#40304)
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2026-09-18 23:37:58 -07:00 |
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5e9342d16f
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[PP][DeepSeek V4] Overlap communication and optimize SM120 prefill (#38792)
Co-authored-by: Yangmin Li <yangminl@nvidia.com>
Co-authored-by: YAMY <74099316+YAMY1234@users.noreply.github.com>
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2026-09-18 21:18:04 -07:00 |
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Cheng Wan
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afe71f4b9e
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Read process groups through the runtime context (#40068)
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2026-09-18 17:40:32 -07:00 |
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5931fd60ee
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Support unified memory page-envelope transfers in PD (#39477)
Co-authored-by: yhzhuang <yhzhuang@fb.com>
Co-authored-by: Lianmin Zheng <lianminzheng@gmail.com>
Co-authored-by: Yonghao Zhuang <yhzhuang@users.noreply.github.com>
Co-authored-by: Cheng Wan <cheng.wan@radixark.ai>
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2026-09-18 17:39:50 -07:00 |
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Jialin Ouyang
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f3851486cb
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[Perf] Fuse SWA page lookup and mapping clear (#38948)
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2026-09-18 15:51:07 -07:00 |
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81a199f56a
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[HiCache] Read the in-flight buffer backup's node id from its snapshot in sanity_check (#40013)
Co-authored-by: Pranjal Shankhdhar <pranjalssh@meta.com>
Co-authored-by: Jialin Ouyang <Jialin.Ouyang@gmail.com>
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2026-09-18 15:47:56 -07:00 |
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Liangsheng Yin
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6cc9090d1f
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[mem_cache] Release up to owned_kv_len on radix cache insert (#40075)
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2026-09-18 15:37:52 -07:00 |
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Zhiqiang Xie
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a0534f8cca
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[HiCache] Stop arming a prefetch retry for a too-short storage span (#40042)
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2026-09-18 15:33:58 -07:00 |
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a6cf05817f
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dsv4.1: remaining model and runtime integration (#38798)
Co-authored-by: BBuf <1182563586@qq.com>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Co-authored-by: Xiaoyu Zhang <xiaoyu.zhang@radixark.ai>
Co-authored-by: Yuwei An <ayw.sirius19@gmail.com>
Co-authored-by: Khoa Pham <khoa.pham@radixark.ai>
Co-authored-by: Yuhao Yang <47235274+yhyang201@users.noreply.github.com>
Co-authored-by: Zhichen Zeng <zczeng@uw.edu>
Co-authored-by: Ke Bao <ispobaoke@gmail.com>
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2026-09-18 02:55:30 -07:00 |
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zhaozx-cn
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8ac39c66d8
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[NPU] support kimi k3 on A5 and improve performance (#39589)
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2026-09-18 16:33:54 +08:00 |
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iridiumine
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f86f60081d
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[NPU] Adapt hicache for K3 hybrid models (#39415)
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2026-09-18 14:48:20 +08:00 |
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Nan Jiang
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20518d8518
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[Scheduler] Align RadixCache no-insert cleanup with kv_len_to_handle (#35204)
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2026-09-17 17:00:59 -07:00 |
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Thomas Wang
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6c73368c32
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[AMD][DSV4] Enable hicache on deepseek-v4 fp8 unified attn (#37778)
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2026-09-17 11:29:23 -07:00 |
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Shuwen Wang
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6ca866ea29
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[HiCache][Perf] fix: batch HiCache D2H submits per step for hybrid pools (#39050)
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2026-09-17 17:53:58 +08:00 |
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yl3469andShuwen Wang
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1a90ae6727
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Add Agentic-Aware Tail-Optimized LRU eviction to the unified radix cache (#34012)
Co-authored-by: Shuwen Wang <47200617+alphabetc1@users.noreply.github.com>
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2026-09-17 17:52:59 +08:00 |
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Teng MaandTeng Ma
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15b256bdb0
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[HiCache] fix: resolve Mooncake local_hostname per node for runtime attach (#29668)
Co-authored-by: Teng Ma <11641725+stmatengss@users.noreply.github.com>
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2026-09-17 15:51:21 +08:00 |
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Michele PalazziandTeng Ma
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329ffc89b9
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[Mooncake] Fix silent SSD offload corruption when TP/PP ranks share ssd_offload_path (#31926)
Signed-off-by: Michele Palazzi <sysdadmin@m1k.cloud>
Co-authored-by: Teng Ma <sima.mt@alibaba-inc.com>
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2026-09-17 10:51:03 +08:00 |
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4793f56835
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[HiCache] Keep hybrid transfer layer maps stage-local under PP (#39699)
Co-authored-by: Aurick Qiao <6137920+aurickq@users.noreply.github.com>
Co-authored-by: Ke Bao <ispobaoke@gmail.com>
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2026-09-17 10:18:44 +08:00 |
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qyb233
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4fb9b5b5ba
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feat(hicache): support NPU Mamba states with FIA and async IO (#32500)
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2026-09-17 10:12:26 +08:00 |
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Shuwen Wang
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4c85172f3a
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[HiCache] Back up MXFP8 KV scales in the host pool (#39089)
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2026-09-17 09:40:26 +08:00 |
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ShunkangzandZhangheng
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e7f7447333
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[kv-shard 2/4] Sharded pools (#37615)
Co-authored-by: Zhangheng <hzh0425@apache.org>
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2026-09-16 19:22:23 +08:00 |
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Jinyan Yi
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dbd7281b06
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fix(npu): fix hybrid KV transfer with PP prefill in PD disaggregation (#38402)
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2026-09-16 09:10:17 +08:00 |
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Zhiqiang Xie
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4e9e407d37
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[HiCache] Label radix-cache metrics per rank and split the "shrunk" prefetch reason (#39280)
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2026-09-15 17:54:04 -07:00 |
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2929a39927
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Use a shared byte budget for unified hybrid-SWA memory (#36729)
Co-authored-by: yhzhuang <yhzhuang@fb.com>
Co-authored-by: Cheng Wan <cheng.wan@radixark.ai>
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2026-09-15 15:27:00 -07:00 |
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Zhiqiang Xie
|
7f5dd19256
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[HiCache] Rework the buffer-mode storage prefetch pipeline and retry bookkeeping (#39283)
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2026-09-15 10:48:49 -07:00 |
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Khoa PhamandClaude Fable 5.1
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2c37b90ad6
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[Fix][DCP] Localize widened KV ids in MLA retraction CPU backup/restore (#39487)
Co-authored-by: Claude Fable 5.1 <noreply@anthropic.com>
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2026-09-15 13:33:41 +08:00 |
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ishandhanani
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3f871a246c
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feat(agent sessions): attribute stored KV cache blocks to sessions (#37482)
Signed-off-by: Ishan Dhanani <ishandhanani@gmail.com>
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2026-09-14 21:34:49 -07:00 |
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cctry
|
dad8c074e7
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Scope prefetch cache state to the request attempt (#39318)
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2026-09-14 15:03:03 -07:00 |
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Kurt Shuster
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f81fbc749a
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[Fix] Merge adjacent KV-row frees so a mid-page split under DCP cannot double-free (#38941)
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2026-09-14 21:44:32 +08:00 |
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amd-danli103
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5aa9b8fb3e
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[AMD][DSV4] feat: enable fp8 two-pool unified_kv on gfx950 (#37413)
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2026-09-14 02:49:11 -07:00 |
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Cheng Xin
|
ca8ecc6a6f
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[NPU] Support DSV4 host memory cache management (#37382)
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2026-09-14 10:38:50 +08:00 |
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Cheng Wan
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2ec4bbcbd4
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[unified-memory] PD disaggregation for every unified pool shape (#37506)
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2026-09-13 19:16:43 -07:00 |
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Shuwen Wang
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ff228d11fe
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[HiCache] Release buffer prefetch anchor locks during storage cleanup (#38483)
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2026-09-13 20:47:21 +00:00 |
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Shuwen WangandClaude Opus 5
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7f1f8c706a
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[mem_cache][10/N] refactor: drop the redundant _component suffix in unified_cache/components (#35644)
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
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2026-09-13 21:38:20 +08:00 |
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Jundong LiuandShuwen Wang
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7078e5ffbc
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[HiCache] Publish a host store event for storage-prefetch refills (#38486)
Co-authored-by: Shuwen Wang <47200617+alphabetc1@users.noreply.github.com>
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2026-09-13 10:29:14 +00:00 |
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huangtingweiandhzh0425
|
a7cf4a6fbc
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[Unified Cache][7/N] Support MTP, EAGLE, and DSpark draft KV caches in the external linker (#37914)
Co-authored-by: hzh0425 <hzh0425@apache.org>
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2026-09-13 18:22:06 +08:00 |
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