 Chunan Zeng
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b66f8e0b96
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Sgl flashmla (#26132)
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2026-05-26 12:00:23 -07:00 |
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+2
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3f5e2c7688
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[AMD] Dsv4/pr2 compressor opt (#26208)
Co-authored-by: wunhuang <wunhuang@amd.com>
Co-authored-by: Thomas Wang <1am9trash@gmail.com>
Co-authored-by: Xinyi Song <86638975+RolaoDenthu@users.noreply.github.com>
Co-authored-by: HaiShaw <hixiao@gmail.com>
Co-authored-by: amd-danli103 <danli103@amd.com>
Co-authored-by: Lin, Soga <soga.lin@amd.com>
Co-authored-by: Raiden-Makoto <Raiden-Makoto@users.noreply.github.com>
Co-authored-by: Hubert Lu <55214931+hubertlu-tw@users.noreply.github.com>
Co-authored-by: yichiche@amd.com <jacky.cheng>
Co-authored-by: yctseng0211 <yctseng@amd.com>
Co-authored-by: Bingxu Chen <bingxche@amd.com>
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2026-05-25 23:54:40 -07:00 |
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Jincong Chen
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e27d4fb70f
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[Perf][Qwen3.5] Add case 512 to topkGatingSoftmaxKernelLauncher, (#25775)
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2026-05-25 16:08:21 +08:00 |
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Ma Mingfei
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821d5f4a5b
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[CPU] add faster KV-cache writes (#25874)
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2026-05-25 10:28:52 +08:00 |
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+2
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af8f66940e
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[AMD] Dsv4/pr1 fix run time issue (#25898)
Co-authored-by: wunhuang <wunhuang@amd.com>
Co-authored-by: Thomas Wang <1am9trash@gmail.com>
Co-authored-by: Xinyi Song <86638975+RolaoDenthu@users.noreply.github.com>
Co-authored-by: HaiShaw <hixiao@gmail.com>
Co-authored-by: amd-danli103 <danli103@amd.com>
Co-authored-by: Lin, Soga <soga.lin@amd.com>
Co-authored-by: Raiden-Makoto <Raiden-Makoto@users.noreply.github.com>
Co-authored-by: Hubert Lu <55214931+hubertlu-tw@users.noreply.github.com>
Co-authored-by: yichiche@amd.com <jacky.cheng>
Co-authored-by: yctseng0211 <yctseng@amd.com>
Co-authored-by: Bingxu Chen <bingxche@amd.com>
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2026-05-23 16:04:14 -07:00 |
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84ea47eb22
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[CPU] Fix issues when running llama3.2-11B vision model with image tasks (#8666)
Co-authored-by: JieXin Liang <Alcanderian@users.noreply.github.com>
Co-authored-by: Yineng Zhang <me@zhyncs.com>
Co-authored-by: jianan-gu <jianan.gu@intel.com>
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2026-05-21 13:09:18 +08:00 |
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Yuan Luoandluoyuan.luo
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b7085d3860
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[fp8] SM90 swap-AB scaled_mm dispatch (~1.16x kernel geomean, +5.8-18.5% end-to-end) (#25532)
Co-authored-by: luoyuan.luo <luoyuan.luo@antgroup.com>
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2026-05-20 13:20:37 +08:00 |
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miamiaoxyzandMa Mingfei
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5147de26e4
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Fix AMX GQA extend attention (#25180)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
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2026-05-18 09:30:02 +08:00 |
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nohup
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34cb8e2842
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fix(sgl-kernel): sm90 compile flashmla failed (#24130)
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2026-05-15 16:42:33 +08:00 |
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897587b03a
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[MUSA]: Add flashinfer sampling backend (#24978)
Co-authored-by: github-actions[bot] <github-actions[bot]@users.noreply.github.com>
Co-authored-by: zhiguo.qin <zhiguo.qin@mthreads.com>
Co-authored-by: R0CKSTAR <yeahdongcn@gmail.com>
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2026-05-14 20:23:15 -07:00 |
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R0CKSTAR
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74d70af09a
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[Apple Silicon] Add Metal kernel support in sgl-kernel (#23449)
Signed-off-by: Xiaodong Ye <yeahdongcn@gmail.com>
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2026-05-11 17:54:27 -07:00 |
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Brayden Zhongandb8zhong
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05d1ab51e8
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Enable PDL for various kernels in DSV32/GLM5 (#23965)
Co-authored-by: b8zhong <b8zhong@users.noreply.github.com>
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2026-05-09 03:42:56 -07:00 |
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Yuxuan Zhang
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d49fc092cb
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[Bug Fix] GLM-5.1: drop constexpr on page_indice_batch_offset, skip offloader post_init on draft worker, support N=32 in copy_to_gpu_no_ce (#23550)
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2026-05-09 15:43:45 +08:00 |
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Yibo Cai
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55d8223c2b
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[sgl-kernel/cpu] support w8a8 int8 model for arm cpu (#16045)
skip gpu test as this one is not related to gpu backend.
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2026-05-08 14:47:06 +08:00 |
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JoeyandR0CKSTAR
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15e6572f21
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[MUSA][18/N] Add MUSA-optimized kernel implementations for hot ops (#23255)
Signed-off-by: Joey-gvwal <joey_gvwal@yeah.net>
Co-authored-by: R0CKSTAR <yeahdongcn@gmail.com>
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2026-05-07 20:38:33 -07:00 |
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Mandepudi Rani ChowdaryandMa Mingfei
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55224fff08
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Add Arm64 CPU Phase 1A CI bootstrap (#22123)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
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2026-05-08 09:28:23 +08:00 |
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10fd0faccd
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[CPU] Add Qwen3.5 model optimization for CPU (#19484)
Co-authored-by: Zheng, Beilei <beilei.zheng@intel.com>
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
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2026-04-26 10:12:36 -07:00 |
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Jia GuoandClaude Opus 4.6
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587fd15bd2
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perf: eliminate attention DtoD copy by passing pre-allocated output to FA (#21985)
Co-authored-by: Claude Opus 4.6 <noreply@anthropic.com>
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2026-04-24 12:05:16 -07:00 |
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Ma Mingfei
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23e4d381f0
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[CPU] remove RECORD_FUNCTION (#23528)
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2026-04-24 09:18:29 +08:00 |
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MARATRIXandAlex Nails
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74c2e5bacd
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[MUSA][8/N] Port CUDA kernels that are compatible with MUSA (#17946)
Signed-off-by: yafeng.li <yafeng.li@mthreads.com>
Co-authored-by: Alex Nails <alex.nails@radixark.ai>
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2026-04-23 18:04:58 -07:00 |
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jianan-guandMa Mingfei
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ad0fc88810
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[CPU] [Quantization] Add GPTQ/AWQ 4bits quantization support for CPU (#22685)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
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2026-04-22 13:34:02 -07:00 |
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Tarushii Goel
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3ebf066d13
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[sgl] update specdec sampling kernel to return valid token ID (#22643)
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2026-04-21 20:28:19 -07:00 |
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Ma Mingfei
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929e00eeab
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[CPU] expand the interface of shared_expert without scaling factor (#22933)
merge since this is CPU only change on sgl-kernel.
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2026-04-21 20:03:39 +08:00 |
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fe9b9b254b
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Fix segfault in cudaMemcpyBatchAsync on CUDA 13.0 (#23136)
Co-authored-by: Claude Opus 4.6 <noreply@anthropic.com>
Co-authored-by: Kangyan-Zhou <zky314343421@gmail.com>
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2026-04-20 12:20:22 -07:00 |
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0dcfae5553
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[CPU] Add gemma4_rmsnorm_cpu kernel (#22842)
Co-authored-by: Copilot <198982749+Copilot@users.noreply.github.com>
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
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2026-04-17 13:03:16 +08:00 |
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Chunyuan WUandMa Mingfei
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6c89214584
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[CPU][sgl-kernel] extend_attention_cpu and flash_attn_varlen_func: fix nan for large seq (#22434)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
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2026-04-17 13:01:01 +08:00 |
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jianan-guandMa Mingfei
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2ab141547d
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[CPU] Add apply_routed_scaling_factor_on_output support for biased_grouped_topk fusion (#22413)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
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2026-04-10 15:16:05 +08:00 |
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Yibo CaiandMa Mingfei
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4644d28213
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[sgl-kernel/cpu] fix build error on non-x86 platform (#22245)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
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2026-04-10 09:58:07 +08:00 |
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Brayden Zhong
|
6aafe756b9
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Revert "[Feature] NVFP4 Marlin fallback for non-Blackwell GPUs (SM75+… (#22047)
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2026-04-03 13:12:30 -07:00 |
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Mook
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991f3aa5b3
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[Feature] NVFP4 Marlin fallback for non-Blackwell GPUs (SM75+) (#19652)
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2026-04-03 10:48:15 +08:00 |
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Xiaoyu Zhang
|
cdd7d6a227
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Remove obsolete sgl-kernel legacy paths (#21528)
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2026-04-01 09:00:20 +08:00 |
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Ma Mingfei
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af62bd9486
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[CPU] Implement MXFP4 Gemm kernels for intel AMX to support GPT OSS series. (#14385)
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2026-03-29 23:44:12 -07:00 |
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blzhengandMa Mingfei
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ed01e1d5d6
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[CPU] add kernel apply_rotary_pos_emb_cpu for Qwen3-VL and Qwen3-Omni (#13121)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
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2026-03-29 23:43:46 -07:00 |
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Ma Mingfei
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6da8f5f69e
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fix topk softmax performance issue (#14702)
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2026-03-29 23:43:16 -07:00 |
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Johnsonms
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8a56a7b04d
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[jit_kernel] Migrate cast (downcast_fp8) from sgl-kernel AOT to JIT (#19103)
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2026-03-27 13:21:44 +08:00 |
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Minglei Zhu
|
a12fea21ed
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perf(sgl-kernel): expose get_scheduler_metadata for FA3 decode optimization (#21103)
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2026-03-25 13:17:27 -07:00 |
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Brayden Zhong
|
009eee85a0
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CUTLASS FP8 Blockwise GEMM improvement of SM120 (#20887)
|
2026-03-22 17:55:54 +08:00 |
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Cao E
|
274581fb77
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Add support for more batch sizes in cpu_graph_runner (#13881)
|
2026-03-19 09:50:56 -07:00 |
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Qi Yuhang
|
cb8105fe28
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[sgl-kernel][6/7]Support Expert Specialization Grouped GEMM (#15471)
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2026-03-19 15:39:52 +08:00 |
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blzhengandFan Yin
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cd22aa27a9
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[CPU] Add FP8 Bmm support (#9744)
Co-authored-by: Fan Yin <1106310035@qq.com>
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2026-03-18 22:19:48 -07:00 |
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blzhengandWu, Chunyuan
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c2b01bd2fc
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[CPU] fix bug in AVX512 implementation of flash_attn_softmax (#20220)
Co-authored-by: Wu, Chunyuan <chunyuan.wu@intel.com>
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2026-03-18 22:18:47 -07:00 |
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Ma Mingfei
|
687d9eb66f
|
[CPU] Optimize image preprocessor performance for Qwen2VLImageProcessorFast (#15168)
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2026-03-18 22:18:15 -07:00 |
|
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Ma Mingfei
|
62d7454976
|
optimize conv3d used in patch embedding (#16040)
|
2026-03-18 22:17:53 -07:00 |
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blzhengandgemini-code-assist[bot]
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cbea9f6909
|
[CPU] improve numa memory binding (#19666)
Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
|
2026-03-18 22:15:50 -07:00 |
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Zaili WangandMa Mingfei
|
2f4babe32b
|
[CPU] support LayerNorm with 3D shape (#15075)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
|
2026-03-18 22:15:24 -07:00 |
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blzhengandMa Mingfei
|
dc6aa26ce9
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[CPU] Add mrope kernel for Qwen3-vl (#12531)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
|
2026-03-18 22:12:48 -07:00 |
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Xiaoyu Zhang
|
25e38216b6
|
[kernel slimming] Clean many useless sgl-kernel deprecated kernels (#20277)
|
2026-03-14 16:45:54 +08:00 |
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|
Mohammad Miadh Angkad
|
f88acf8780
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[JIT Kernel] Reland NVFP4 kernels to JIT (#20012)
|
2026-03-07 10:31:08 +08:00 |
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Baizhou Zhang
|
51e5dc845a
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Revert "[Kernel Slimming] Migrate NVFP4 kernels to JIT" (#20005)
|
2026-03-05 19:40:00 -08:00 |
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Mohammad Miadh Angkad
|
2bdd89a6cd
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[Kernel Slimming] Migrate NVFP4 kernels to JIT (#19437)
|
2026-03-05 15:22:28 +08:00 |
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