 Khoa PhamandQiaolin Yu
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018b73c7a0
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[PD] Pack draft KV head slices for DCP transfers (#40500)
Co-authored-by: Qiaolin Yu <liin1211@outlook.com>
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2026-09-21 21:11:27 -07:00 |
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b44e248682
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[AMD] [GLM-5.3-Flash Day 0] Enable FP8 and Quark MXFP4 MoE on gfx950 (#38546)
Co-authored-by: Raiden-Makoto <Raiden-Makoto@users.noreply.github.com>
Co-authored-by: Thomas Wang <thomawan@amd.com>
Co-authored-by: andyluo7 <andy.luo@amd.com>
Co-authored-by: Kevin Mi <mikevin920@yahoo.com>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
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2026-09-21 21:07:37 -07:00 |
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jthomson04
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15ba54bd5d
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perf(engine): avoid timed waits for Engine responses (#39486)
Signed-off-by: jthomson04 <jwillthomson19@gmail.com>
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2026-09-21 20:42:03 -07:00 |
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Jan BernlöhrandPo-Han Huang
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56fee88e23
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fix(moe): support Llama4 NVFP4 router input weights on SM120 (#35504)
Co-authored-by: Po-Han Huang (NVIDIA) <53919306+nvpohanh@users.noreply.github.com>
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2026-09-21 20:18:11 -07:00 |
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90cf471723
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[AMD] [GLM-5.3-Flash Day 0] Support non-2048 top-k widths in the DSA page-table transform (#39340)
Co-authored-by: Thomas Wang <thomawan@amd.com>
Co-authored-by: Kevin Mi <45493463+kevin-mii@users.noreply.github.com>
Co-authored-by: Kevin Mi <mikevin920@yahoo.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
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2026-09-21 19:50:17 -07:00 |
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5f9c6b9eb0
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[diffusion] fix: separate a use-scoped layerwise release from release_all (#40590)
Co-authored-by: Mick Qian <mickqian@users.noreply.github.com>
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
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2026-09-22 10:38:44 +08:00 |
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MickandMick Qian
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a1b2b976fe
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[diffusion] CI: restore public Qwen-Image 2.1 TP2 E2E coverage (#40507)
Co-authored-by: Mick Qian <mickqian@users.noreply.github.com>
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2026-09-22 10:38:00 +08:00 |
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Yuhan Zhou
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15eba3b464
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Feat: Add TensorCast storage as a new HiCache backend (#27265)
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2026-09-22 10:19:04 +08:00 |
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jacky.cheng
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bc30fa1759
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[AMD][Fix] AgentX HIP TPOT regression when SGLANG_SIMULATE_ACC_LEN is set (#40598)
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2026-09-21 19:16:15 -07:00 |
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Mohammad Miadh Angkadandmmangkad
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e332e1b84e
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[Fix] Don't write conv state from the fused KDA verify kernel (#39524)
Co-authored-by: mmangkad <mohammad.angkad@radixark.ai>
|
2026-09-21 18:33:03 -07:00 |
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Dayananda VandClaude Opus 5
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35eb7cf8d6
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[Intel][XPU][KVCanary] Enable KV Canary on Intel XPU (#33520)
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
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2026-09-22 09:19:01 +08:00 |
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Khoa Pham
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c4d3770a68
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[Kimi K3] Fix CUDA graph stream explosion (#40640)
|
2026-09-21 17:49:50 -07:00 |
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jacky.cheng
|
31b577bb08
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[AMD] Pad QSA MQA decode Q-heads to 16 for ROCm MFMA (#38875)
|
2026-09-21 17:43:46 -07:00 |
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042b6a488f
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[AMD] [GLM-5.3-Flash Day 0] Enable zero-RoPE MHA prefill on ROCm (#39338)
Co-authored-by: Thomas Wang <thomawan@amd.com>
Co-authored-by: Kevin Mi <45493463+kevin-mii@users.noreply.github.com>
|
2026-09-21 17:38:07 -07:00 |
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Cheng Wan
|
582389cec5
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[Fix] Keep diffusion encoder TP context bindings consistent (#40646)
|
2026-09-21 17:23:15 -07:00 |
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Tao LiandXiaoyu Zhang
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c53cc8e1eb
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[NPU][BugFix] Avoid M-RoPE recompilation for variable sequence lengths (#40371)
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
|
2026-09-22 08:19:25 +08:00 |
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avalliappan-nvidia
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61d0cf2074
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[Spec] Windowed draft-decode attention for built-in EAGLE / MTP drafts (#32673)
|
2026-09-22 08:17:57 +08:00 |
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Vedant V JhaveriandCopilot
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9fdb71732a
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Avoid materializing GDN QKV tensors during target verification (#33778)
Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
|
2026-09-21 17:04:18 -07:00 |
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Cheng Wan
|
506698761d
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[unified-memory] Hierarchical cache for every unified pool shape (#37507)
|
2026-09-21 16:50:37 -07:00 |
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Cheng Wan
|
22587fb15c
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[Fix] Run KV canary hooks for context-parallel prefill (#40642)
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2026-09-21 16:46:22 -07:00 |
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Yuxuan ZhangandXinyuan Tong
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00986c81be
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Support GLM-5.3-Flash hybrid attention CPU offload and PD index mapping (#40310)
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
|
2026-09-21 16:03:03 -07:00 |
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YAMY
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0229025127
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[Spec][PP] Launch extend microbatches before the spec output exchange (#40499)
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2026-09-21 15:47:03 -07:00 |
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RuibinCheung
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0c53fec476
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[ROCm] fix: remove extra bf16 -> fp32 cast in jit grouped topk kernel path (#39775)
|
2026-09-21 15:43:21 -07:00 |
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8bde82c0ad
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[AMD] [GLM-5.3-Flash Day 0] Build the fused DSA k-pool top-k JIT kernel on HIP (#39339)
Co-authored-by: Raiden-Makoto <Raiden-Makoto@users.noreply.github.com>
Co-authored-by: Thomas Wang <thomawan@amd.com>
Co-authored-by: Kevin Mi <mikevin920@yahoo.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
|
2026-09-21 15:24:44 -07:00 |
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Cheng Wan
|
acac4dd9d9
|
[Refactor] Clean up parallel runtime comments (#40632)
|
2026-09-21 14:32:22 -07:00 |
|
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William Hu
|
f532ad1f9a
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Fix GLM-5.3 forget-gate shape for nvCUTEDSL verify (#40607)
|
2026-09-21 13:52:26 -07:00 |
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jacky.cheng
|
e0c2e8dc4d
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[AMD] Tune Qwen3.5 TP4 GDN recurrent launch on gfx950 (#39987)
|
2026-09-21 13:20:54 -07:00 |
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Liangsheng Yin
|
b18ca9ca44
|
[CI] Bump sgl-eval to 0.1.2 (#40620)
|
2026-09-21 13:00:54 -07:00 |
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11e661fd45
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[Fix] Don't free the multi-CTAs KV counter the decode graphs captured (#39175)
Co-authored-by: mmangkad <mohammad.angkad@radixark.ai>
Co-authored-by: kpham-sgl <khoa.pham@radixark.ai>
Co-authored-by: Claude Fable 5.1 <noreply@anthropic.com>
|
2026-09-21 12:58:48 -07:00 |
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Cheng Wan
|
bccf691b22
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Bringing the parallel runtime up becomes a phase, not a side effect (#40345)
|
2026-09-21 12:29:50 -07:00 |
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Cheng Wan
|
1d3243d05f
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Take the parallel getters off the package's public surface (#40344)
|
2026-09-21 12:27:50 -07:00 |
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Cheng Wan
|
970e946e4f
|
Retire the per-runner parallel record (#40343)
|
2026-09-21 12:26:40 -07:00 |
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Cheng Wan
|
73f071db52
|
Deprecate the parallel getters the context answers, and ratchet them shut (#40342)
|
2026-09-21 12:25:32 -07:00 |
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Cheng Wan
|
65be3fa71a
|
A runner and the objects it builds freeze the placement they describe (#40341)
|
2026-09-21 12:24:17 -07:00 |
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|
Cheng Wan
|
2d0e94e3a3
|
Check the topology identities where the layout is written, and build at the published widths (#40340)
|
2026-09-21 12:22:59 -07:00 |
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Cheng Wan
|
0db1a93adb
|
State the draft's whole topology in its scope, and read the rest from the context (#40339)
|
2026-09-21 12:19:38 -07:00 |
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ae7a516ba7
|
feat: use XGrammar V4.1 DSML parameter constraints (#39026)
Co-authored-by: yuchuan <yuchuan.7streams@gmail.com>
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
|
2026-09-21 12:12:28 -07:00 |
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jacky.cheng
|
90b3f8544c
|
[AMD] Use Triton softmax routing for Qwen3.5 on gfx950 (#39986)
|
2026-09-21 12:02:29 -07:00 |
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|
ronnie_zheng
|
f702a0be29
|
Revert "[Diffusion] migrate the whole _register_configs from registry.py to the model own config file" (#40611)
|
2026-09-21 21:05:19 +03:00 |
|
|
Bingxu Chen
|
632919e498
|
[AMD] Fix DeepSeek-R1-MXFP4 accuracy with AITER FP8 (#37762)
|
2026-09-21 10:51:37 -07:00 |
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ronnie_zheng
|
e6931ca889
|
[Diffusion] migrate the whole _register_configs from registry.py to the model own config file (#40475)
|
2026-09-21 20:45:53 +03:00 |
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cctry
|
7a6191c4b9
|
Preallocate HiCache MHA staging before post-capture KV sizing (#40256)
|
2026-09-21 10:44:29 -07:00 |
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cctry
|
7ad55e4386
|
[HiCache] TMA-staged host<->device KV transfer kernel (sm_90+) (#40278)
|
2026-09-21 10:38:23 -07:00 |
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|
William Hu
|
0cb37c018c
|
[KDA] Enable ReplaySSM for GLM-5.3 Flash (#40517)
|
2026-09-21 10:34:08 -07:00 |
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Eric.Chin.AMDandThomas Wang
|
3c71bb018a
|
[AMD] Enable GLM DSA prefill top-k to the v2 kernel (#37889)
Co-authored-by: Thomas Wang <thomawan@amd.com>
|
2026-09-21 10:31:07 -07:00 |
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|
|
5a6a1bb883
|
[mxfp8-kv] Skip writes to the reserved CUDA-graph padding slot (#35351)
Co-authored-by: Claude Opus 4.8 <noreply@anthropic.com>
Co-authored-by: Ke Bao <ispobaoke@gmail.com>
Co-authored-by: Sam Shleifer <sam@thinkingmachines.ai>
|
2026-09-22 01:21:25 +08:00 |
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Liangsheng Yin
|
800613a74b
|
[Test] Split the serving perf tests by topic into basic_perf/ and route their thresholds through a kit (#40505)
|
2026-09-21 10:05:57 -07:00 |
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|
Sage
|
14e9c40a72
|
[Observability] Expose python/rust frontend identity in /server_info (#39993)
Signed-off-by: Sage Ahrac <sagiahrak@gmail.com>
|
2026-09-21 23:32:52 +08:00 |
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|
hanwlax
|
8faa2d6731
|
[NPU][Diffusion] Disable loading latency checks in Ascend fixtures (#40544)
|
2026-09-21 16:56:35 +08:00 |
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|
Mohammad Miadh AngkadandMohammad Angkad
|
8d08dfdab7
|
[Fix] Add gigachat35 to the tool-call and reasoning parser name lists (#40554)
Co-authored-by: Mohammad Angkad <mohammad.angkad@radixark.ai>
|
2026-09-21 16:34:43 +08:00 |
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