 MickandMick Qian
|
00a9028e87
|
[diffusion] feat: add explicit snapshot-offload component residency (#38535)
Co-authored-by: Mick Qian <mickqian@users.noreply.github.com>
|
2026-09-09 13:44:54 +08:00 |
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Ankith AverineniandHaiShaw
|
eb42598bdd
|
[AMD][DSV4] Skip the paged SWA page return under the per-request ring (#38571)
Co-authored-by: HaiShaw <hixiao@gmail.com>
|
2026-09-08 21:15:30 -07:00 |
|
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Xiaoyu Zhang
|
2952c8d5ea
|
[Diffusion] Fuse LongCat Image normalization and modulation (#38530)
|
2026-09-09 11:12:17 +08:00 |
|
|
Alison Shao
|
76eea36e38
|
Cast fp32 routing weights to bf16 in the Kimi-K3 fused finalize (#38588)
|
2026-09-09 10:48:21 +08:00 |
|
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Jialin Ouyang
|
7a464a7014
|
[Rust TreeCore] Harden runtime and CI parity (#37303)
|
2026-09-09 10:40:22 +08:00 |
|
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Baizhou Zhang
|
e54ff1efb9
|
[CP V1 Deprecation 5/5] Update prefill CP documentation (#36230)
|
2026-09-08 19:27:49 -07:00 |
|
|
James
|
8ab9982851
|
[NPU]support mf device urma and host rdma trans type (#38174)
|
2026-09-09 09:44:19 +08:00 |
|
|
DayuxiaoshuiandXiaoyu Zhang
|
db1de6ff4c
|
[Diffusion] Keep the Wan VAE decoder channels_last and add a Triton NHWC nearest upsample (#38182)
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
|
2026-09-09 09:31:35 +08:00 |
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|
YanbingJiang
|
a67a31aa81
|
[CPU] Support Qwen3.8 text+video: adding torchcodec, ffmpeg and removing pin_memory (#35492)
|
2026-09-09 09:22:58 +08:00 |
|
|
jianan-gu
|
da821aad11
|
[XPU][Diffusion] Enable MiniMax H3 on XPU platforms (#33366)
|
2026-09-09 09:20:04 +08:00 |
|
|
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295132c4a5
|
[NPU] Add sparsity-driven KV offload for DeepSeek DSA on Ascend (#33089)
Co-authored-by: itcj <itcj@foxmail.com>
Co-authored-by: chenyh <chenyh18@mail.ustc.edu.cn>
Co-authored-by: hibikid <7514545+hibikid@user.noreply.gitee.com>
Co-authored-by: Chengjie Tang <tangcj@sxu.edu.cn>
Co-authored-by: wangbiao0814 <wangbiao0814@outlook.com>
|
2026-09-09 09:13:22 +08:00 |
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MickandMick Qian
|
a8e45f16cc
|
[diffusion] feat: support mixed INT8 embeddings and Comfy NVFP4 encoders for minimax-h3 (#38506)
Co-authored-by: Mick Qian <mickqian@users.noreply.github.com>
|
2026-09-09 08:36:43 +08:00 |
|
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MickandMick Qian
|
65400bb420
|
[diffusion] model: support MiniMax-H3 singularity hybrid checkpoints (#38455)
Co-authored-by: Mick Qian <mickqian@users.noreply.github.com>
|
2026-09-09 08:35:39 +08:00 |
|
|
Cheng Wan
|
db272201a2
|
[Config] Retire get_global_server_args, and clear the deprecated flags that have a replacement (#38375)
|
2026-09-08 16:42:12 -07:00 |
|
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Chunan ZengandKevin Mi
|
5177a3ec08
|
MiniMax-M3: Triton split-K router GEMV with in-kernel fixup (#36557)
Co-authored-by: Kevin Mi <45493463+kevin-mii@users.noreply.github.com>
|
2026-09-08 16:39:41 -07:00 |
|
|
Chunan ZengandKevin Mi
|
a25bbca8ed
|
MiniMax-M3: share the sparse index top-k across layers and reuse the decode top-k buffer (#36527)
Co-authored-by: Kevin Mi <mikevin920@yahoo.com>
|
2026-09-08 16:39:01 -07:00 |
|
|
Baizhou Zhang
|
ed183d45ac
|
[CP V1 Deprecation 4/5] Canonicalize prefill CP API names (#36229)
|
2026-09-08 16:03:36 -07:00 |
|
|
Qiaolin Yu
|
559c7fa75b
|
Revert "PD disaggregation, isolated transfer, prefill OOM fixed." (#38572)
|
2026-09-08 15:57:44 -07:00 |
|
|
+3
|
52fecfdf09
|
support qwen 3.8 flash next (#37500)
Co-authored-by: ch-wan <54331508+ch-wan@users.noreply.github.com>
Co-authored-by: ispobock <26454835+ispobock@users.noreply.github.com>
Co-authored-by: JustinTong0323 <115166877+JustinTong0323@users.noreply.github.com>
Co-authored-by: samuellees <26428561+samuellees@users.noreply.github.com>
Co-authored-by: YAMY1234 <74099316+YAMY1234@users.noreply.github.com>
Co-authored-by: yhyang201 <47235274+yhyang201@users.noreply.github.com>
Co-authored-by: yizhang2077 <25844240+yizhang2077@users.noreply.github.com>
Co-authored-by: zijiexia <37504505+zijiexia@users.noreply.github.com>
Co-authored-by: Shinto C V <cshintov@gmail.com>
Co-authored-by: Julian Huang <huangzhilin.hzl@antgroup.com>
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
Co-authored-by: yhyang201 <yhyang201@gmail.com>
|
2026-09-08 13:56:21 -07:00 |
|
|
Brayden ZhongandBrayden Zhong
|
30e7a3072d
|
Keep fp32 routing weights in the fp8 block-scale and bf16 trtllm MoE (#33631)
Co-authored-by: Brayden Zhong <brayden@radixark.ai>
|
2026-09-08 08:56:40 -07:00 |
|
|
HZYandZhangheng
|
8a0863c728
|
[HiCache] Add MLA host-dedup primitives (#36800)
Co-authored-by: Zhangheng <hzh0425@apache.org>
|
2026-09-08 23:40:21 +08:00 |
|
|
|
325ab245a1
|
[DCP] Allow fi_a2a on single-node systems Blackwell without MNNVL fabric ( ex B200 B300) (#37767)
Co-authored-by: Hao Phan <htphan@nvidia.com>
Co-authored-by: Khoa Pham <khoa.pham@radixark.ai>
|
2026-09-08 07:55:36 -07:00 |
|
|
Liu Ziming
|
beecfda314
|
[observability] Fix missing e2e/decode/inference latency span attributes (#37789)
|
2026-09-08 22:50:55 +08:00 |
|
|
|
15ff470472
|
[diffusion] chore: key the VAE decode-dtype store by module layout (#38496)
Co-authored-by: Mick Qian <mickqian@radixark.ai>
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
|
2026-09-08 22:37:21 +08:00 |
|
|
HZY
|
a6b542813f
|
fix(glm-5.2-nvfp4): bound Mooncake synchronous transfer batches (#32758)
|
2026-09-08 22:14:33 +08:00 |
|
|
SovietPowerandXiaoyu Zhang
|
4df5df911b
|
[Scheduler] Add HRRN schedule policy to significantly reduce TTFT (#32911)
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
|
2026-09-08 22:14:03 +08:00 |
|
|
Po-Han Huang (NVIDIA)
|
5097f9ac95
|
Disable Hopper GLM shared-expert fusion for modelopt_fp4 Marlin (#37325)
|
2026-09-08 06:16:36 -07:00 |
|
|
Xiaoyu Zhang
|
554f817948
|
[Diffusion] Optimize LTX-2 QKNorm and split RoPE on Hopper (#38396)
|
2026-09-08 19:05:02 +08:00 |
|
|
|
88a9bfd1ff
|
[diffusion] CI: add per-case timing tolerance for host-I/O-bound perf guards (#38457)
Co-authored-by: Mick Qian <mickqian@radixark.ai>
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
|
2026-09-08 18:40:17 +08:00 |
|
|
zijiecandZijie Chen
|
e634ba78a4
|
[AMD] gfx950 assembly attention for EAGLE verify, draft extend and decode (#37465)
Co-authored-by: Zijie Chen <300606707+zijiecode@users.noreply.github.com>
|
2026-09-08 03:10:09 -07:00 |
|
|
amd-danli103
|
141febf329
|
[AMD] fix: use the hardware fp8 e4m3 convert on gfx950 (#37140)
Signed-off-by: amd-danli103 <danli103@amd.com>
|
2026-09-08 03:01:53 -07:00 |
|
|
|
775f17b07c
|
[diffusion] optimization: stream mapped weights on a shared host/device pool (#38441)
Co-authored-by: Mick Qian <mickqian@radixark.ai>
Co-authored-by: Claude Fable 5.1 <noreply@anthropic.com>
|
2026-09-08 17:52:52 +08:00 |
|
|
vorapolsiloai
|
7edcdd5ae6
|
[AMD] Skip AITER FP8 ASM prefill when GQA is unsupported (#38467)
|
2026-09-08 02:49:47 -07:00 |
|
|
Hank Han
|
ccfa120dae
|
Fix DSA compression tail capacity for PD decode request slots (#38417)
|
2026-09-08 01:50:07 -07:00 |
|
|
cen121212
|
f8f03910f2
|
【NPU】Support EAGLE when PP enabled in prefill nodes (#32207)
|
2026-09-08 15:45:36 +08:00 |
|
|
Sage
|
5aab054ec8
|
[rust-server] fix p/d bootstrap across dp listeners (#36234)
|
2026-09-08 13:22:32 +08:00 |
|
|
Shuwen Wang
|
61d501427d
|
fix: make dfs weight ordering iterative (#38313)
|
2026-09-08 05:10:22 +00:00 |
|
|
Anupa Sajikumar
|
91a45ea37e
|
[Intel][XPU][LoRA] Enable LoRA on Intel XPU (#30345)
|
2026-09-08 12:46:41 +08:00 |
|
|
Liwansiandsglang-npu-bot
|
92371e9887
|
PD disaggregation, isolated transfer, prefill OOM fixed. (#38094)
Co-authored-by: sglang-npu-bot <sglangnpu@163.com>
|
2026-09-08 11:44:35 +08:00 |
|
|
Wuhen Duan
|
dfd9b5c2a4
|
[NPU] Enable non-greedy MTP sampling (#32495)
|
2026-09-08 11:18:01 +08:00 |
|
|
Liangsheng Yin
|
28ebede865
|
[mem_cache] Free hybrid SWA pages by one representative per page on page_size > 1 (#38159)
|
2026-09-07 20:15:54 -07:00 |
|
|
Liangsheng Yin
|
b23d835048
|
[Scheduler] Unify per-iteration request intake into ingest_requests() (#38389)
|
2026-09-07 20:02:02 -07:00 |
|
|
Xinguo Zhu
|
2bf04f3a67
|
[Diffusion][CPU] Enable MiniMax-H3 on Xeon CPU (#35147)
|
2026-09-08 10:56:42 +08:00 |
|
|
Polisetty V R K Jyothendra Varma
|
cf35384fe4
|
[Intel GPU] Add MLA support to Intel XPU Attention backend for Prefill (#35866)
Signed-off-by: P V R K Jyothendra Varma <polisetty.v.r.k.jyothendra.varma@intel.com>
|
2026-09-08 10:29:28 +08:00 |
|
|
HZY
|
8656901504
|
[Fix][DSA] Bound prefill Triton specializations for page-table stride (#37093)
|
2026-09-08 10:23:51 +08:00 |
|
|
Chao Shiandhuangtingwei9988
|
e31e5319a0
|
HiCache: Reduce the number of all_reduce in check_hicache_events for PP (#37562)
Co-authored-by: huangtingwei9988 <huangtingwei.htw@antgroup.com>
|
2026-09-08 10:13:22 +08:00 |
|
|
|
fba967ed9c
|
[diffusion] Support diffusion decoder parallel tiling for LTX-2.5 (#36026)
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
Co-authored-by: Mick Qian <mickqian@users.noreply.github.com>
|
2026-09-08 10:01:06 +08:00 |
|
|
Siju Samuel
|
2358916d5a
|
[Feature][Intel XPU] Add memory saver support for Intel XPU via upstream torch_memory_saver (#29935)
|
2026-09-08 09:38:51 +08:00 |
|
|
qyb233
|
c72cae201e
|
[NPU] Fix ViT graph key layout handling (#37758)
|
2026-09-08 09:21:02 +08:00 |
|
|
|
5aa913e156
|
[AMD][GLM-5.2] Keep GlmMoeDsa MoE e_score_correction_bias in fp32 (#37133)
Co-authored-by: JohnQinAMD <yanyuan.qin@amd.com>
Co-authored-by: Thomas Wang <thomawan@amd.com>
Co-authored-by: Zhang, Jiejing <jiejing.zhang@amd.com>
|
2026-09-07 18:17:54 -07:00 |
|