18675 Commits
Author SHA1 Message Date
Jimmy Shong daade9cc00 [Fix] Probe speculative draft config via sglang get_config (#25428) 2026-05-15 22:01:44 -07:00
Mick 416fdbbb3d [diffusion] feat: generalize layerwise offload residency mixin to all components (#24593) 2026-05-16 11:44:46 +08:00
Jimmy Shong a741d0cc56 [CI] Lower mem-fraction-static for GLM-5.1 FP8 8-GPU test to 0.85 (#25453) 2026-05-15 20:14:47 -07:00
Sam Shleifer ce2506e1c6 Deprecate record_nolora_graph dual MoE CUDA graph capture (#24314) 2026-05-15 19:20:58 -07:00
Liangsheng Yin b674007026 [CI] Show distinct run-name per event in pr-test workflow (#25452) 2026-05-15 18:58:07 -07:00
fzyzcjy 4c6eb12dea Fix invalid suite name in test_multi_detokenizer (#25450) 2026-05-16 09:42:11 +08:00
fzyzcjy 688b679af2 Convert discarded-value ternary to a plain if statement (#25449) 2026-05-16 09:35:36 +08:00
Liangsheng Yin b7d62bd724 [CI] Rename basic CI stage-a/b/c -> base-a/b/c for symmetry with extra CI (#25420) 2026-05-15 18:26:55 -07:00
fzyzcjy d0c38329b2 Inline the trivial _build_model_config wrapper (#25448) 2026-05-16 09:25:48 +08:00
fzyzcjy 4190328767 Replace defensive getattr in pool_configurator with direct access (#25447) 2026-05-16 09:25:14 +08:00
fzyzcjy 48f85d464f Fix V2 trace filename collisions when DP/PP/EP enabled (#25446) 2026-05-16 09:24:39 +08:00
fzyzcjy b3059e2d1e Inject ParallelState into ProfilerV2 (#25445) 2026-05-16 09:24:15 +08:00
fzyzcjy 43797cc804 Bundle Scheduler rank/size fields into a frozen ParallelState (#25444) 2026-05-16 09:23:51 +08:00
fzyzcjy 7c716e73e0 Add mechanical-refactor-verify skill from miles (#25443) 2026-05-16 09:23:06 +08:00
fzyzcjy fa8b7c9647 Lift forward_ct/cur_batch and use direct access in watchdog (#25442) 2026-05-16 09:22:41 +08:00
fzyzcjy 72eb231d28 Annotate dead max_running_requests_under_SLO (#25441) 2026-05-16 09:22:13 +08:00
fzyzcjy c8e5cf5768 Fix LoRA pool not appearing in /v1/loads (#25440) 2026-05-16 09:21:27 +08:00
fzyzcjy 5c440cdc41 Lift running_batch / running_mbs access — direct + PP-explicit (#25439) 2026-05-16 09:21:00 +08:00
fzyzcjy 80c3ce3204 Convert forward_pass_device_timer to None-init (#25438) 2026-05-16 09:20:31 +08:00
Lianmin ZhengandHanming Lu 21e420b4c2 [Test] Set default temperature to 0.0 in kl_test_utils (#25429)
Co-authored-by: Hanming Lu <69857889+hanming-lu@users.noreply.github.com>
2026-05-15 18:20:10 -07:00
fzyzcjy 40429248c8 Drop dead hasattr guards (hisparse_coordinator, metrics_collector) (#25437) 2026-05-16 09:19:56 +08:00
fzyzcjy 0071033ff6 Cache _linear_attn_registry_cache with sentinel (#25436) 2026-05-16 09:19:21 +08:00
fzyzcjy 6a1b05d706 Replace single-line defensive getattrs with direct access (#25435) 2026-05-16 09:18:43 +08:00
fzyzcjy 27c3190215 Remove fields that are never used in spec/engine/disagg (#25434) 2026-05-16 09:18:00 +08:00
fzyzcjy e065445236 Remove managers' unused fields (#25433) 2026-05-16 09:17:11 +08:00
fzyzcjy 33d63aa7e1 Remove dead self.adder/can_run_list/running_bs writes in Scheduler._get_new_batch_prefill_raw (#25432) 2026-05-16 09:12:39 +08:00
fzyzcjy 824ad24149 Convert local-only self.X attributes to locals (#25430) 2026-05-16 09:05:43 +08:00
Yuhao Yang 18c16f8660 Port SGLANG_OPT_SWA_EVICT_DROP_PAGE_MARGIN from deepseek_v4_dev (#25419) 2026-05-15 17:39:13 -07:00
Brayden Zhongandb8zhong d523ae127f Fix Mistral Large 3 nightly test (#25407)
Co-authored-by: b8zhong <b8zhong@users.noreply.github.com>
2026-05-15 17:28:35 -07:00
5ba69f50fb Add multi-detokenizer support (#24944)
Co-authored-by: ybyang <10629930+whybeyoung@users.noreply.github.com>
Co-authored-by: Shangming Cai <csmthu@gmail.com>
2026-05-15 17:26:26 -07:00
Hanming Lu afc7c9f7f3 [TRTLLM/SWA/Spec] fix trtllm mha + swa + spec accept length drop (#25103) 2026-05-15 17:15:31 -07:00
jasonjk-park 3c2956d880 Add extension points on SpeculativeAlgorithm for custom spec v2 (#24999) 2026-05-15 15:45:31 -07:00
Xinyuan Tong 7cb4669a04 [Fix] DeepSeek-V3.2: build structural tag locally to encode both wrapper and invoke layers (#25233) 2026-05-15 14:32:50 -07:00
Liangsheng Yin 494ee71189 split test_dsa_models_mtp into 4 files (#25318) 2026-05-15 14:16:57 -07:00
Liangsheng Yin f9caf43095 [CI] slash handler: lookup runs_on from runner_configs.yml (#25394) 2026-05-15 13:59:00 -07:00
Cheng WanandClaude Opus 4.7 54221dd998 feat(moe): reuse prev-layer output as symm_output for FP4 routed MoE (#25379)
Co-authored-by: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
2026-05-15 12:05:40 -07:00
Xinyuan Tong 33f1d3915f [NEW MODEL] Add H200 validation for Ring-2.6-1T cookbook (#25370) 2026-05-15 11:47:15 -07:00
Alex Nails 4df42da658 Introduce CudaDeviceMixin and CudaSRTPlatform (#24096) 2026-05-15 10:59:02 -07:00
Cheng WanandClaude Opus 4.7 ee93795476 perf(mla): hybrid Triton fused cat+FP8-quantize for MLA chunked-prefill K/V (#25333)
Co-authored-by: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
2026-05-15 10:51:00 -07:00
Kai-Hsun ChenandClaude Opus 4.7 17c8a2fa53 [Llama4] Use strided in-place fused QK RMSNorm to drop a redundant copy (#25089)
Co-authored-by: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
2026-05-15 10:33:08 -07:00
Zhangheng 21b3ac52b4 [UnifiedTree]: Fix UnifiedRadixCache device match semantics with HiCache (#25277) 2026-05-16 00:40:55 +08:00
Cheng Wan 3f7e538b2f Add NPU condition for cosine and sine caching (#25399) 2026-05-15 05:21:53 -07:00
Liangsheng Yin fd9525436b move runs_on + rdma into runner_configs.yml (#25264) 2026-05-15 04:19:13 -07:00
Liangsheng Yin 293027aafa pr-states: fix fork-PR token + add run-ci label awareness (#25392) 2026-05-15 04:09:15 -07:00
Liangsheng Yin 3117415c9b ci: standalone PR awareness workflow (decouple from pr-test reusable chain) (#25387) 2026-05-15 03:20:00 -07:00
Chi McIsaac 20123e0b16 [diffusion] fix: mount Cache-DiT before torch.compile in native denoising (#25328) 2026-05-15 18:08:39 +08:00
liuxianglong17 eec5ba26cf Fix incorrect import in test case (#25080) 2026-05-15 17:35:57 +08:00
Liangsheng Yin eff736cc0f Deprecate /rerun-stage; scrub CUDA target_stage infra (#25322) 2026-05-15 02:18:28 -07:00
Baizhou Zhang 1a1d69507d [Doc] Update MegaMoE usage (#25378) 2026-05-15 02:17:50 -07:00
Zhangheng fe7a5dd3bf [UnifiedTree]: Add nightly hicache ci for dsa model (#25348) 2026-05-15 16:54:50 +08:00