 desmond-intel
|
6dc7b3421b
|
Inference Support Mamba 2 and 1 (#34556)
|
2026-09-12 20:51:18 +08:00 |
|
|
Vignesh Sethuraman
|
ddf02a4f58
|
[AMD] aiter: resolve SWA KV pool for draft workers + guard paged decode (#38756)
|
2026-09-11 10:13:48 -07:00 |
|
|
Vignesh Sethuraman
|
76ef679cb1
|
[AMD] aiter: fail loudly on cross-layer KV sharing in target_verify (#38755)
|
2026-09-10 23:37:03 -07:00 |
|
|
|
02236fa38c
|
Add Inkling model support (#31681)
Co-authored-by: Chunan Zeng <zcnrex@gmail.com>
Co-authored-by: Ke Bao <ispobaoke@gmail.com>
Co-authored-by: Yanbin Jiang <jybsuper@gmail.com>
Co-authored-by: Yuhao Yang <47235274+yhyang201@users.noreply.github.com>
Co-authored-by: Qiaolin Yu <qiaolin.yu@radixark.ai>
Co-authored-by: Zhichen Zeng <zczeng@uw.edu>
Co-authored-by: Aurick Qiao <aurick@thinkingmachines.ai>
Co-authored-by: Joseph <jk@thinkingmachines.ai>
|
2026-07-19 22:57:37 -07:00 |
|
|
sglang-botandClaude Sonnet 4.6
|
3d922a51fc
|
test: remove multimodal piecewise CUDA graph gate test (#29537)
Co-authored-by: Claude Sonnet 4.6 (1M context) <noreply@anthropic.com>
|
2026-06-27 19:03:32 -07:00 |
|
|
zijiexiaandClaude Opus 4.8
|
669be5448b
|
[cuda graph] Enable prefill piecewise CUDA graph for Cohere2Vision (text path) (#28686)
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
|
2026-06-22 19:20:14 +00:00 |
|
|
Lianmin Zheng
|
95fb1ef697
|
[CI] Remove deprecated test/srt legacy CI setup (#28810)
|
2026-06-20 15:09:33 -07:00 |
|
|
Yuan Luoandluoyuan.luo
|
3340f4e3da
|
[GDN][KDA][mem_cache] int8 checkpoint pool for the linear-attn prefix cache (#28185)
Co-authored-by: luoyuan.luo <luoyuan.luo@antgroup.com>
|
2026-06-17 20:41:46 -07:00 |
|
|
Mandepudi Rani Chowdary
|
7e3e616159
|
Add Arm64 INT8 MoE test coverage (#25007)
|
2026-06-10 10:36:57 +08:00 |
|
|
Zaili WangandMa Mingfei
|
3b7a258f63
|
[CPU] upgrade dependent torch ver to PT2.12 (#21456)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
|
2026-06-04 11:04:11 +08:00 |
|
|
|
3ecf2c76ad
|
[CPU] Add GPT-OSS model optimization for CPU (#16775)
Co-authored-by: mingfeima <mingfei.ma@intel.com>
Co-authored-by: jianan-gu <jianan.gu@intel.com>
|
2026-05-29 16:05:26 +08:00 |
|
|
MingxuZh
|
21ba329dac
|
[Xeon] CPU CI enhancement for Intel Xeon platforms (#24649)
|
2026-05-28 10:49:04 +08:00 |
|
|
vikram singh shekhawatandMa Mingfei
|
737c6cd6d1
|
[XPU] Add registry mechanism for XPU CI tests (#25405)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
|
2026-05-27 08:56:59 +08:00 |
|
|
Liangsheng Yin
|
d7e3e54148
|
[Test] split test/registered/distributed/ into topic folders (#26240)
|
2026-05-24 17:02:07 -07:00 |
|
|
|
84ea47eb22
|
[CPU] Fix issues when running llama3.2-11B vision model with image tasks (#8666)
Co-authored-by: JieXin Liang <Alcanderian@users.noreply.github.com>
Co-authored-by: Yineng Zhang <me@zhyncs.com>
Co-authored-by: jianan-gu <jianan.gu@intel.com>
|
2026-05-21 13:09:18 +08:00 |
|
|
miamiaoxyzandMa Mingfei
|
5147de26e4
|
Fix AMX GQA extend attention (#25180)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
|
2026-05-18 09:30:02 +08:00 |
|
|
Liangsheng Yin
|
b7d62bd724
|
[CI] Rename basic CI stage-a/b/c -> base-a/b/c for symmetry with extra CI (#25420)
|
2026-05-15 18:26:55 -07:00 |
|
|
Mandepudi Rani ChowdaryandMa Mingfei
|
55224fff08
|
Add Arm64 CPU Phase 1A CI bootstrap (#22123)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
|
2026-05-08 09:28:23 +08:00 |
|
|
|
da7f890788
|
[Intel GPU] Integrate flash_mla_decode in Intel XPU attention backend (#23557)
Signed-off-by: P V R K Jyothendra Varma <polisetty.v.r.k.jyothendra.varma@intel.com>
Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
Co-authored-by: Kangyan-Zhou <zky314343421@gmail.com>
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
|
2026-05-01 07:21:28 +08:00 |
|
|
Lianmin Zheng
|
b1ef99f65f
|
[CI] Remove orphaned test/srt/ascend and test/srt/configs (#24145)
|
2026-04-30 04:43:11 -07:00 |
|
|
MingxuZhandMa Mingfei
|
2d27c38f13
|
Update XPU Docker runtime stack & hf_home config (#23820)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
|
2026-04-29 10:03:11 +08:00 |
|
|
|
10fd0faccd
|
[CPU] Add Qwen3.5 model optimization for CPU (#19484)
Co-authored-by: Zheng, Beilei <beilei.zheng@intel.com>
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
|
2026-04-26 10:12:36 -07:00 |
|
|
jianan-guandMa Mingfei
|
ad0fc88810
|
[CPU] [Quantization] Add GPTQ/AWQ 4bits quantization support for CPU (#22685)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
|
2026-04-22 13:34:02 -07:00 |
|
|
Ma Mingfei
|
929e00eeab
|
[CPU] expand the interface of shared_expert without scaling factor (#22933)
merge since this is CPU only change on sgl-kernel.
|
2026-04-21 20:03:39 +08:00 |
|
|
|
f63def8510
|
[XPU] Fix DeepSeek-OCR tests under transformers 5.x (#23044)
Co-authored-by: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
|
2026-04-21 14:57:56 +08:00 |
|
|
|
0dcfae5553
|
[CPU] Add gemma4_rmsnorm_cpu kernel (#22842)
Co-authored-by: Copilot <198982749+Copilot@users.noreply.github.com>
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
|
2026-04-17 13:03:16 +08:00 |
|
|
Chunyuan WUandMa Mingfei
|
6c89214584
|
[CPU][sgl-kernel] extend_attention_cpu and flash_attn_varlen_func: fix nan for large seq (#22434)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
|
2026-04-17 13:01:01 +08:00 |
|
|
Baizhou ZhangandClaude Opus 4.6
|
3c46ff2ac5
|
fix: restore CPU flash_attn test to use sgl_kernel directly (#22573)
Co-authored-by: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
|
2026-04-10 21:39:20 -07:00 |
|
|
jianan-guandMa Mingfei
|
2ab141547d
|
[CPU] Add apply_routed_scaling_factor_on_output support for biased_grouped_topk fusion (#22413)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
|
2026-04-10 15:16:05 +08:00 |
|
|
Sundara Raman Ramachandran
|
a64905a7b8
|
[CICD] [prefill-only] Consolidate prefill-only model E2E tests (#22405)
|
2026-04-09 00:54:34 -07:00 |
|
|
Sundara Raman Ramachandran
|
712c8c5051
|
[Score API] Add SequenceClassification Model support (#22118)
|
2026-04-08 01:30:58 -07:00 |
|
|
Rain Jiang
|
1a8eb890f6
|
Kernels community fa3 (#20796)
|
2026-04-07 12:48:44 -07:00 |
|
|
Huaiyu, Zheng
|
68f4c52d34
|
fix ut test_moe (#21735)
|
2026-04-03 21:57:11 -07:00 |
|
|
Baizhou ZhangandClaude Opus 4.6
|
29d8e959d7
|
[CI] Remove stale Ascend suite entries from test/srt/run_suite.py (#21978)
Co-authored-by: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
|
2026-04-02 16:47:19 -07:00 |
|
|
Cherry_ming
|
e67b95d66b
|
[NPU]Add a full test pipeline on NPU, resolve issues in the NPU test architecture (#20751)
|
2026-04-01 19:56:31 +08:00 |
|
|
blzhengandMa Mingfei
|
ed01e1d5d6
|
[CPU] add kernel apply_rotary_pos_emb_cpu for Qwen3-VL and Qwen3-Omni (#13121)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
|
2026-03-29 23:43:46 -07:00 |
|
|
Lianmin ZhengandClaude Opus 4.6
|
27ac831a84
|
docs: improve CI and testing documentation (#21202)
Co-authored-by: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
|
2026-03-23 10:48:50 -07:00 |
|
|
Cao E
|
274581fb77
|
Add support for more batch sizes in cpu_graph_runner (#13881)
|
2026-03-19 09:50:56 -07:00 |
|
|
blzhengandFan Yin
|
cd22aa27a9
|
[CPU] Add FP8 Bmm support (#9744)
Co-authored-by: Fan Yin <1106310035@qq.com>
|
2026-03-18 22:19:48 -07:00 |
|
|
blzhengandWu, Chunyuan
|
c2b01bd2fc
|
[CPU] fix bug in AVX512 implementation of flash_attn_softmax (#20220)
Co-authored-by: Wu, Chunyuan <chunyuan.wu@intel.com>
|
2026-03-18 22:18:47 -07:00 |
|
|
Zaili WangandMa Mingfei
|
2f4babe32b
|
[CPU] support LayerNorm with 3D shape (#15075)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
|
2026-03-18 22:15:24 -07:00 |
|
|
blzhengandMa Mingfei
|
dc6aa26ce9
|
[CPU] Add mrope kernel for Qwen3-vl (#12531)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
|
2026-03-18 22:12:48 -07:00 |
|
|
Juan MunetonandKangyan-Zhou
|
4052b53227
|
fix scheduler for non-cuda devices and disable piecewise cuda graph f… (#19992)
Co-authored-by: Kangyan-Zhou <zky314343421@gmail.com>
|
2026-03-18 21:54:19 -07:00 |
|
|
Juan MunetonandYang Wang
|
7458407437
|
Fix InternVL and vision attention for non-CUDA backends (e.g. XPU) (#19997)
Co-authored-by: Yang Wang <mr.yang.wang@outlook.com>
|
2026-03-14 23:24:41 -07:00 |
|
|
SoluMilken
|
c95dc88f86
|
[CI] migrate ascend-gptq from test/srt to test/registered (#19628)
|
2026-03-14 00:28:57 -07:00 |
|
|
|
11b76d24dc
|
[NPU] [DLLM]DLLM LLaDA2.x graph mode support with NPU speedup modifications (#18485)
Co-authored-by: Zhang-Xiaoxue <xiaoxuezhang17@outlook.com>
Co-authored-by: dawncc <dawn.cc022@gmail.com>
Co-authored-by: lixinqi7 <li_xinqi7@163.com>
Co-authored-by: rangejay <rangejay1st@163.com>
|
2026-03-09 22:41:05 +08:00 |
|
|
|
13bdc7bf4a
|
[Feature][NPU]: add runtime support for AutoRound quantized models (#16699)
Co-authored-by: root <root@localhost.localdomain>
Co-authored-by: ronnie_zheng <zl19940307@163.com>
|
2026-03-07 18:03:55 +03:00 |
|
|
|
6910c1b281
|
[Feature][NPU]: add runtime support for GPTQ-quantized MoE models (#16364)
Co-authored-by: GuoYechang <52730608+GuoYechang@users.noreply.github.com>
Co-authored-by: root <root@localhost.localdomain>
|
2026-03-04 16:02:19 +03:00 |
|
|
Alison ShaoandAlison Shao
|
eb6bcc5c86
|
[CI] Register test_quant_config_parsing.py in CI suite (#19809)
Co-authored-by: Alison Shao <alisonshao@Mac.attlocal.net>
|
2026-03-03 16:53:31 -08:00 |
|
|
Praneth Paruchuriandgemini-code-assist[bot]
|
f7897def96
|
[Feature] Improve weight loading log (#18651)
Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
|
2026-03-03 14:16:13 -08:00 |
|