 Pai Liu
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cf1fd26d16
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benchmark/lora: make number of LoRA adapters configurable (#25363)
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2026-05-20 18:23:13 -07:00 |
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Lifu Huang
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ce832d7034
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Add env var to control custom Triton kernel cache and set CSGMV as default backend. (#12176)
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2025-10-27 17:49:32 -07:00 |
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Yineng Zhang
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da681f35d3
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Revert "Set csgmv as default lora backend. (#11488)" (#11735)
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2025-10-17 12:01:36 -05:00 |
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Lifu Huang
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b0d20cdec7
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Set csgmv as default lora backend. (#11488)
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2025-10-15 23:53:24 -05:00 |
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Yuan Luoandluoyuan.luo
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590f2da052
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[Feat] Support Torch Symm Mem AllReduce (#10571)
Co-authored-by: luoyuan.luo <luoyuan.luo@antgroup.com>
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2025-10-05 13:55:19 -07:00 |
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zyksir
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8e3797be1c
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support 1 shot allreduce in 1-node and 2-node using mscclpp (#6277)
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2025-06-04 22:11:24 -07:00 |
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Qiaolin YuandBeichen Ma
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8c0cfca87d
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Feat: support cuda graph for LoRA (#4115)
Co-authored-by: Beichen Ma <mabeichen12@gmail.com>
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2025-04-28 23:30:44 -07:00 |
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588865f0e0
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[Feature] Support Tensor Parallelism and Weight Slicing for Lora (#4274)
Co-authored-by: ShenAo1111 <1377693092@qq.com>
Co-authored-by: Baizhou Zhang <sobereddiezhang@gmail.com>
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2025-03-18 20:33:07 -07:00 |
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Baizhou ZhangandYing Sheng
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70817a7eae
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[Feature] Define backends and add Triton backend for Lora (#3161)
Co-authored-by: Ying Sheng <sqy1415@gmail.com>
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2025-02-03 22:09:13 -08:00 |
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Ying Sheng
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9c064bf78a
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[LoRA, Performance] Speedup multi-LoRA serving - Step 1 (#1587)
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2024-10-06 10:33:44 -07:00 |
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Ying Sheng
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37963394aa
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[Feature] Support LoRA path renaming and add LoRA serving benchmarks (#1433)
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2024-09-15 12:46:04 -07:00 |
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