 Cheng Wan
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2d0e94e3a3
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Check the topology identities where the layout is written, and build at the published widths (#40340)
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2026-09-21 12:22:59 -07:00 |
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e8e765b9d6
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[AMD] Add fused all-reduce RMSNorm per-group quant for Qwen3.5 FP8 (#24651)
Co-authored-by: jacky.cheng <yichiche@amd.com>
Co-authored-by: yctseng0211 <yctseng@amd.com>
Co-authored-by: HAI <hixiao@gmail.com>
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2026-07-22 07:33:03 -07:00 |
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c2eae96c56
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MSCCL++ Integration (#22734)
Co-authored-by: Caio Rocha <caiorocha@microsof.com>
Co-authored-by: empyreus <rjsouza1995@gmail.com>
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2026-06-08 21:13:13 -07:00 |
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Hubert LuandHAI
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edaa5973d4
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[AMD][No-Merge] Simplify fused allreduce + RMSNorm and remove hidden_dim allowlist (#21986)
Co-authored-by: HAI <hixiao@gmail.com>
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2026-04-11 23:47:08 -07:00 |
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Lianmin Zheng
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104b10f70a
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refactor: consolidate is_in_ci (jit_kernel, sgl-kernel benchmarks, tests) (#21009)
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2026-03-20 05:55:36 -07:00 |
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Hubert Luandyctseng0211
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17b0affbdf
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[AMD] Support --enable-aiter-allreduce-fusion on AMD GPUs (#13747)
Co-authored-by: yctseng0211 <yctseng@amd.com>
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2026-02-24 23:11:55 -08:00 |
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Yuan Luoandluoyuan.luo
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7bb41989fa
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[1/N] Optimize All Reduce - Benchmark different AR operations (#13797)
Co-authored-by: luoyuan.luo <luoyuan.luo@antgroup.com>
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2026-01-26 22:44:13 +08:00 |
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e4b2937017
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[AMD] Add AITER Custom All-Reduce (#13102)
Co-authored-by: Brayden Zhong <b8zhong@uwaterloo.ca>
Co-authored-by: HaiShaw <hixiao@gmail.com>
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2025-11-12 21:53:44 -08:00 |
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Yuan Luoandluoyuan.luo
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819fc59123
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Add prefix for torch symm mem (#12506)
Co-authored-by: luoyuan.luo <luoyuan.luo@antgroup.com>
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2025-11-02 11:23:05 -08:00 |
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Yuan Luoandluoyuan.luo
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590f2da052
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[Feat] Support Torch Symm Mem AllReduce (#10571)
Co-authored-by: luoyuan.luo <luoyuan.luo@antgroup.com>
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2025-10-05 13:55:19 -07:00 |
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zyksir
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8e3797be1c
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support 1 shot allreduce in 1-node and 2-node using mscclpp (#6277)
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2025-06-04 22:11:24 -07:00 |
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