[AMD] Fix deepseek-v4 mtp accept length issue (#28520)
Co-authored-by: Bingxu Chen <bingxche@amd.com>
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co-authored by
Bingxu Chen
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8aaca72c21
commit
f5b041622b
@@ -1316,24 +1316,37 @@ class DeepseekV4HipRadixBackend(
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recompute at store time, matching the pre-cache per-layer behavior, for
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paths that never ran the decode-stream init (eager prefill/extend, idle,
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or a batch re-padded after init -> shape mismatch).
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Cached swa_loc is computed once from committed positions, so every draft-decode
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step would reuse the same ring slot and break the chain. Recompute from the live
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per-step positions; only the draft path is affected, the rest keeps the fast path.
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"""
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positions = forward_batch.positions
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core = getattr(self.forward_metadata, "core_attn_metadata", None)
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unified = getattr(core, "unified", None) if core is not None else None
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cached = unified.swa_loc if unified is not None else None
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is_multistep_draft_decode = (
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forward_batch.forward_mode.is_decode_or_idle()
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and self.speculative_num_steps > 1
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)
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if (
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cached is not None
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and not forward_batch.forward_mode.is_idle()
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and cached.shape[0] == positions.shape[0]
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and not is_multistep_draft_decode
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):
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return cached
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ring = self.token_to_kv_pool.unified_swa_ring_size
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req_slot = forward_batch.req_pool_indices.to(torch.int64)
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if req_slot.shape[0] != positions.shape[0]:
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req_slot = req_slot.repeat_interleave(
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positions.shape[0] // req_slot.shape[0]
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result = cached
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else:
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ring = self.token_to_kv_pool.unified_swa_ring_size
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req_slot = forward_batch.req_pool_indices.to(torch.int64)
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if req_slot.shape[0] != positions.shape[0]:
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req_slot = req_slot.repeat_interleave(
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positions.shape[0] // req_slot.shape[0]
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)
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result = (req_slot * ring + positions.to(torch.int64) % ring).to(
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torch.int32
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)
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return (req_slot * ring + positions.to(torch.int64) % ring).to(torch.int32)
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return result
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def store_cache(
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self, layer_id: int, swa_k: torch.Tensor, forward_batch: ForwardBatch
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