Add compile-time 256-bit vector guard for pre-Blackwell (#19794)

python/sglang/jit_kernel/include/sgl_kernel/utils.cuh

@@ -106,6 +106,11 @@ static_assert(
 #define SGL_ARCH_BLACKWELL_OR_GREATER 0
 #endif
 
+// Maximum vector size in bytes supported by current architecture.
+// Pre-Blackwell / AMD: 128-bit (16 bytes)
+// Blackwell or greater: 256-bit (32 bytes)
+inline constexpr std::size_t kMaxVecBytes = SGL_ARCH_BLACKWELL_OR_GREATER ? 32 : 16;
+
 /// \brief Number of threads per warp (always 32 on NVIDIA/AMD GPUs).
 inline constexpr auto kWarpThreads = 32u;
 /// \brief Full warp active mask (all 32 lanes).

python/sglang/jit_kernel/include/sgl_kernel/vec.cuh

@@ -73,8 +73,10 @@ struct alignas(sizeof(T) * N) AlignedStorage {
 template <typename T, std::size_t N>
 struct AlignedVector {
  private:
-  /// NOTE: N must be a power of two and sizeof(T) * N <= 32 bytes (256 bits)
-  static_assert((N > 0 && (N & (N - 1)) == 0) && sizeof(T) * N <= 32, "CUDA only supports at most 256-bit vector op");
+  static_assert(
+      (N > 0 && (N & (N - 1)) == 0) && sizeof(T) * N <= kMaxVecBytes,
+      "CUDA vector size exceeds arch limit: max 16 bytes on pre-Blackwell/AMD, "
+      "32 bytes on Blackwell or greater");
   using element_t = typename details::sized_int<T>;
   using storage_t = AlignedStorage<element_t, N>;