From f28ce5c42094d70dffca0f722dbfd726edf7f8a3 Mon Sep 17 00:00:00 2001
From: "Swift.Sun" <sunjiwei@yeah.net>
Date: Thu, 16 Jul 2026 10:30:01 +0800
Subject: [PATCH] [XPU]REPO cache dtype xpu align with cuda (#31140)

---
 python/sglang/srt/layers/rotary_embedding/base.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/python/sglang/srt/layers/rotary_embedding/base.py b/python/sglang/srt/layers/rotary_embedding/base.py
index 72e693b66..2f68e4965 100644
--- a/python/sglang/srt/layers/rotary_embedding/base.py
+++ b/python/sglang/srt/layers/rotary_embedding/base.py
@@ -95,7 +95,7 @@ class RotaryEmbedding(MultiPlatformOp):
 
         cache = self._compute_cos_sin_cache()
         # NOTE(ByronHsu): cache needs to be in FP32 for numerical stability.
-        if not (_is_cuda or envs.SGLANG_ROPE_CACHE_FP32.get()):
+        if not (_is_cuda or _is_xpu or envs.SGLANG_ROPE_CACHE_FP32.get()):
             cache = cache.to(dtype)
 
         if (