From ece02ffc9cc32e94382d4f1b553b2c755f83f722 Mon Sep 17 00:00:00 2001 From: McZyWu Date: Sat, 18 Jul 2026 21:49:37 +0800 Subject: [PATCH] [NPU] FIX CMB illusion of garbled characters acc problems, in prefix cache mtp scenarios. (#31659) --- .../ascend_hybrid_linear_attn_backend.py | 23 +++++++++++++------ 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/python/sglang/srt/hardware_backend/npu/attention/ascend_hybrid_linear_attn_backend.py b/python/sglang/srt/hardware_backend/npu/attention/ascend_hybrid_linear_attn_backend.py index e1935dc11..2a628c286 100644 --- a/python/sglang/srt/hardware_backend/npu/attention/ascend_hybrid_linear_attn_backend.py +++ b/python/sglang/srt/hardware_backend/npu/attention/ascend_hybrid_linear_attn_backend.py @@ -265,13 +265,22 @@ class AscendHybridLinearAttnBackend(HybridLinearAttnBackend): ) last_steps = last_correct_step_indices.to(torch.int64) # [N] - move_intermediate_cache( - ssm_states, - intermediate_state_cache, - dst_indices_tensor, - src_indices_tensor, - last_steps, - ) + # NPU: skip intermediate_ssm copy when accept_lens == 1. + # The state at step 0 is the just-computed recurrent state, which + # is already correct in the model's ssm buffer. The intermediate + # cache path exists for CUDA's per-step gather; on NPU the fused + # kernel may produce slightly different bfloat16 rounding that + # accumulates over thousands of decode steps and drifts into + # garbage output. + all_step0 = (last_steps == 0).all().item() + if not all_step0: + move_intermediate_cache( + ssm_states, + intermediate_state_cache, + dst_indices_tensor, + src_indices_tensor, + last_steps, + ) draft_token_num = intermediate_state_cache.shape[2] if mamba_track_indices is not None: