[jit-kernel] Support per token group quant 8bit v2 jit kernel (#27449)
Co-authored-by: luoyuan.luo <luoyuan.luo@antgroup.com>
This commit is contained in:
Yuan Luo
@@ -0,0 +1,531 @@
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// JIT port of the AOT sgl_per_token_group_quant_8bit_v2 (sgl-kernel).
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//
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// Same math as the AOT v2 kernel (256-bit vectorized loads, 8 threads/128-group,
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// PDL, NaiveScheduler + MaskedLayoutScheduler, ue8m0/float scales, fp8/int8
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// output, fused silu+mul) so it is a drop-in replacement; the only changes vs the
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// AOT source are the launcher (tvm::ffi::TensorView + TensorMatcher + the JIT
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// LaunchKernel/PDL helpers) and the FP8 type alias.
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#include <sgl_kernel/tensor.h> // TensorMatcher, SymbolicSize/Device
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#include <sgl_kernel/utils.h> // RuntimeCheck, Panic
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#include <sgl_kernel/utils.cuh> // LaunchKernel, fp8_e4m3_t, SGL_DEVICE, device::PDLWaitPrimary/TriggerSecondary
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#include <sgl_kernel/warp.cuh> // device::warp::reduce_max
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#include <tvm/ffi/container/tensor.h>
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#include <cstdint>
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#include <cuda_fp8.h>
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#include <type_traits>
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namespace {
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constexpr float LOCAL_ABSMAX_ABS = 1e-10f;
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constexpr uint32_t INPUT_PRIMARY_VEC_NUM_BYTES = 32;
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template <int THREADS_PER_SUBWARP>
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SGL_DEVICE float GroupReduceMax(float val) {
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static_assert(
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(THREADS_PER_SUBWARP & (THREADS_PER_SUBWARP - 1)) == 0 && THREADS_PER_SUBWARP <= 16 && THREADS_PER_SUBWARP >= 1,
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"THREADS_PER_SUBWARP must be 1, 2, 4, 8, or 16");
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// Reduce within this thread's contiguous THREADS_PER_SUBWARP-lane subgroup via
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// the shared warp primitive, but pass an explicit subgroup mask instead of its
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// default 0xffffffff: the block can be < 32 lanes (subwarps_per_block *
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// THREADS_PER_SUBWARP, e.g. 1..16), where a full-warp mask names non-existent
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// lanes and is UB / can hang.
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constexpr device::warp::mask_t kSub = (device::warp::mask_t{1} << THREADS_PER_SUBWARP) - 1;
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const device::warp::mask_t mask = kSub << (THREADS_PER_SUBWARP * ((threadIdx.x % 32) / THREADS_PER_SUBWARP));
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return device::warp::reduce_max<THREADS_PER_SUBWARP>(val, mask);
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}
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SGL_DEVICE float silu(const float& val) {
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// Match the AOT v2 kernel: tanh-based silu on SM100+ (Blackwell), exp-based
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// elsewhere, so the fused silu+mul output stays bit-identical to the AOT op.
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#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)
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float half = 0.5f * val;
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float t = __tanhf(half);
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return half * (1.0f + t);
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#else
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return val / (1.0f + __expf(-val));
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#endif
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}
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SGL_DEVICE float2 fmul2_rn(float2 a, float2 b) {
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// Match the AOT v2 kernel: use the __fmul2_rn intrinsic on SM100+.
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#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)
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return __fmul2_rn(a, b);
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#else
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float2 result;
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result.x = a.x * b.x;
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result.y = a.y * b.y;
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return result;
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#endif
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}
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// Copied from DeepEP.
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SGL_DEVICE float fast_pow2(int x) {
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uint32_t bits_x = (x + 127) << 23;
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return __uint_as_float(bits_x); // type-safe bit cast (no strict-aliasing UB)
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}
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SGL_DEVICE int fast_log2_ceil(float x) {
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auto bits_x = __float_as_uint(x); // type-safe bit cast (no strict-aliasing UB)
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auto exp_x = (bits_x >> 23) & 0xff;
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auto man_bits = bits_x & ((1 << 23) - 1);
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return exp_x - 127 + (man_bits != 0);
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}
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template <typename T>
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struct DtypeInfo;
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template <>
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struct DtypeInfo<int8_t> {
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static constexpr float MIN = -128;
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static constexpr float MAX = 127;
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};
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template <>
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struct DtypeInfo<fp8_e4m3_t> {
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static constexpr float MIN = -448;
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static constexpr float MAX = 448;
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};
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template <bool ROUND_SCALE, typename dtype_info>
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SGL_DEVICE void calculate_fp8_scales(float amax, float& scale, float& scale_inv) {
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constexpr float MAX_8BIT_INV = 1.0f / dtype_info::MAX;
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if constexpr (ROUND_SCALE) {
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auto exp_scale_inv = fast_log2_ceil(amax * MAX_8BIT_INV);
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scale = fast_pow2(-exp_scale_inv);
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scale_inv = fast_pow2(exp_scale_inv);
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} else {
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scale_inv = amax * MAX_8BIT_INV;
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scale = dtype_info::MAX / amax;
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}
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}
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template <bool SCALE_UE8M0, typename OUT_DTYPE_T = std::conditional_t<SCALE_UE8M0, uint8_t, float>>
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SGL_DEVICE OUT_DTYPE_T extract_required_scale_format(float value) {
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if constexpr (SCALE_UE8M0) {
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return static_cast<uint8_t>(__float_as_uint(value) >> 23);
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} else {
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return value;
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}
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}
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template <bool FUSE_SILU_AND_MUL>
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SGL_DEVICE int compute_input_group_start_offset(
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int expert_idx,
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int token_idx,
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int hidden_dim_group_idx,
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int hidden_size,
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int num_tokens_per_expert,
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int group_size) {
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return expert_idx * num_tokens_per_expert * hidden_size * (FUSE_SILU_AND_MUL ? 2 : 1) +
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token_idx * hidden_size * (FUSE_SILU_AND_MUL ? 2 : 1) + hidden_dim_group_idx * group_size;
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}
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struct NaiveScheduler {
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static void compute_exec_config(
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int threads_per_subwarp,
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int num_local_experts,
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int hidden_dim_num_groups,
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int num_groups,
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int& subwarps_per_block,
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dim3& grid,
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dim3& block) {
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subwarps_per_block = (num_groups % 16 == 0) ? 16
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: (num_groups % 8 == 0) ? 8
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: (num_groups % 4 == 0) ? 4
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: (num_groups % 2 == 0) ? 2
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: 1;
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grid = dim3(num_groups / subwarps_per_block);
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block = dim3(subwarps_per_block * threads_per_subwarp);
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}
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template <bool FUSE_SILU_AND_MUL, int GROUP_SIZE, int THREADS_PER_SUBWARP, typename FUNC>
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SGL_DEVICE static void execute(
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const int subwarps_per_block,
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const int hidden_dim_num_groups,
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const int32_t* masked_m,
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const int num_tokens_per_expert,
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FUNC fn) {
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constexpr int expert_idx = 0;
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const int64_t subwarp_id = threadIdx.x / THREADS_PER_SUBWARP;
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const int lane_id = threadIdx.x % THREADS_PER_SUBWARP;
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const int64_t group_id = static_cast<int64_t>(blockIdx.x) * subwarps_per_block + subwarp_id;
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int64_t input_group_start_offset;
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if constexpr (!FUSE_SILU_AND_MUL) input_group_start_offset = group_id * GROUP_SIZE;
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const int token_idx = group_id / hidden_dim_num_groups;
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const int hidden_dim_group_idx = group_id % hidden_dim_num_groups;
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if constexpr (FUSE_SILU_AND_MUL) {
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const int hidden_size = hidden_dim_num_groups * GROUP_SIZE;
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input_group_start_offset = compute_input_group_start_offset<FUSE_SILU_AND_MUL>(
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expert_idx, token_idx, hidden_dim_group_idx, hidden_size, num_tokens_per_expert, GROUP_SIZE);
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}
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fn(expert_idx, token_idx, hidden_dim_group_idx, lane_id, input_group_start_offset);
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}
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};
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struct MaskedLayoutScheduler {
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static constexpr int TOKEN_DIM_BLOCK_NUM_PER_EXPERT = 1024;
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static constexpr int SUBWARPS_PER_BLOCK = 16;
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static void compute_exec_config(
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int threads_per_subwarp,
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int num_local_experts,
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int hidden_dim_num_groups,
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int num_groups,
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int& subwarps_per_block,
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dim3& grid,
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dim3& block) {
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subwarps_per_block = SUBWARPS_PER_BLOCK;
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host::RuntimeCheck(hidden_dim_num_groups % subwarps_per_block == 0, "hidden_dim_num_groups not divisible by 16");
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grid = dim3(hidden_dim_num_groups / subwarps_per_block, TOKEN_DIM_BLOCK_NUM_PER_EXPERT, num_local_experts);
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block = dim3(subwarps_per_block * threads_per_subwarp);
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}
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template <bool FUSE_SILU_AND_MUL, int GROUP_SIZE, int THREADS_PER_SUBWARP, typename FUNC>
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SGL_DEVICE static void execute(
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const int subwarps_per_block,
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const int hidden_dim_num_groups,
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const int32_t* masked_m,
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const int num_tokens_per_expert,
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FUNC fn) {
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const int64_t subwarp_id = threadIdx.x / THREADS_PER_SUBWARP;
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const int lane_id = threadIdx.x % THREADS_PER_SUBWARP;
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const int expert_idx = blockIdx.z;
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const int token_idx_start = blockIdx.y;
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const int64_t hidden_dim_group_idx = static_cast<int64_t>(blockIdx.x) * SUBWARPS_PER_BLOCK + subwarp_id;
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const int curr_expert_token_num = masked_m[expert_idx];
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for (int token_idx = token_idx_start; token_idx < curr_expert_token_num;
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token_idx += TOKEN_DIM_BLOCK_NUM_PER_EXPERT) {
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const int hidden_size = hidden_dim_num_groups * GROUP_SIZE;
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const int64_t input_group_start_offset = compute_input_group_start_offset<FUSE_SILU_AND_MUL>(
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expert_idx, token_idx, hidden_dim_group_idx, hidden_size, num_tokens_per_expert, GROUP_SIZE);
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fn(expert_idx, token_idx, hidden_dim_group_idx, lane_id, input_group_start_offset);
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}
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}
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};
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template <
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typename SCHEDULER,
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int GROUP_SIZE,
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int THREADS_PER_SUBWARP,
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typename T,
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typename DST_DTYPE,
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bool IS_COLUMN_MAJOR,
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bool SCALE_UE8M0,
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bool FUSE_SILU_AND_MUL,
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bool kUsePDL,
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typename scale_packed_t = std::conditional_t<SCALE_UE8M0, uint32_t, float>>
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__global__ void per_token_group_quant_8bit_v2_kernel(
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const T* __restrict__ input,
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DST_DTYPE* __restrict__ output_q,
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scale_packed_t* __restrict__ output_s,
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const int32_t* __restrict__ masked_m,
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const int subwarps_per_block,
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const int hidden_dim_num_groups,
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const int scale_expert_stride,
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const int scale_hidden_stride,
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const int num_tokens_per_expert) {
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using dst_dtype_info = DtypeInfo<DST_DTYPE>;
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using scale_element_t = std::conditional_t<SCALE_UE8M0, uint8_t, float>;
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static_assert(sizeof(scale_packed_t) % sizeof(scale_element_t) == 0);
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device::PDLWaitPrimary<kUsePDL>();
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SCHEDULER::template execute<FUSE_SILU_AND_MUL, GROUP_SIZE, THREADS_PER_SUBWARP>(
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subwarps_per_block,
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hidden_dim_num_groups,
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masked_m,
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num_tokens_per_expert,
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[&](const int expert_idx,
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const int token_idx,
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const int hidden_dim_group_idx,
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const int lane_id,
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const int input_group_start_offset) {
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constexpr uint32_t INPUT_PRIMARY_VEC_SIZE = INPUT_PRIMARY_VEC_NUM_BYTES / sizeof(T);
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constexpr uint32_t INPUT_PRIMARY_INT4_SIZE = INPUT_PRIMARY_VEC_NUM_BYTES / sizeof(int4);
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const int offset_num_groups = expert_idx * num_tokens_per_expert * hidden_dim_num_groups +
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token_idx * hidden_dim_num_groups + hidden_dim_group_idx;
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int4 input_primary_int4[INPUT_PRIMARY_INT4_SIZE];
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T* input_primary_vec = reinterpret_cast<T*>(input_primary_int4);
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int4 input_secondary_int4[INPUT_PRIMARY_INT4_SIZE];
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T* input_secondary_vec = reinterpret_cast<T*>(input_secondary_int4);
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#pragma unroll
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for (uint32_t j = 0; j < INPUT_PRIMARY_INT4_SIZE; ++j) {
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// Ordinary 128-bit vectorized load (LDG.128); .nc gave no measurable
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// gain on this streaming read-once kernel, so no inline asm.
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input_primary_int4[j] =
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reinterpret_cast<const int4*>(input + input_group_start_offset + lane_id * INPUT_PRIMARY_VEC_SIZE)[j];
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}
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if constexpr (FUSE_SILU_AND_MUL) {
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const int secondary_offset = hidden_dim_num_groups * GROUP_SIZE;
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#pragma unroll
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for (uint32_t j = 0; j < INPUT_PRIMARY_INT4_SIZE; ++j) {
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input_secondary_int4[j] = reinterpret_cast<const int4*>(
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input + input_group_start_offset + lane_id * INPUT_PRIMARY_VEC_SIZE + secondary_offset)[j];
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}
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}
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constexpr int num_elems_per_pack = static_cast<int>(sizeof(scale_packed_t) / sizeof(scale_element_t));
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scale_element_t* scale_output;
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if constexpr (IS_COLUMN_MAJOR) {
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constexpr int scale_token_stride = 1;
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const int hidden_idx_packed = hidden_dim_group_idx / num_elems_per_pack;
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const int pack_idx = hidden_dim_group_idx % num_elems_per_pack;
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scale_output = reinterpret_cast<scale_element_t*>(output_s) +
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(expert_idx * scale_expert_stride * num_elems_per_pack +
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hidden_idx_packed * scale_hidden_stride * num_elems_per_pack +
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token_idx * scale_token_stride * num_elems_per_pack + pack_idx);
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} else {
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static_assert(!SCALE_UE8M0);
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scale_output = output_s + offset_num_groups;
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}
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if constexpr (IS_COLUMN_MAJOR and SCALE_UE8M0) {
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const int remainder_num_groups = hidden_dim_num_groups % num_elems_per_pack;
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if ((remainder_num_groups != 0) and (hidden_dim_group_idx == hidden_dim_num_groups - 1) and
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(lane_id < num_elems_per_pack - remainder_num_groups)) {
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const int shift = 1 + lane_id;
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*(scale_output + shift) = 0;
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}
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}
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float local_absmax = LOCAL_ABSMAX_ABS;
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#pragma unroll
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for (uint32_t j = 0; j < INPUT_PRIMARY_VEC_SIZE; ++j) {
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float val;
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if constexpr (FUSE_SILU_AND_MUL) {
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T val_lowprec = static_cast<T>(silu(static_cast<float>(input_primary_vec[j]))) * input_secondary_vec[j];
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val = static_cast<float>(val_lowprec);
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input_primary_vec[j] = val_lowprec;
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} else {
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val = static_cast<float>(input_primary_vec[j]);
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}
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local_absmax = fmaxf(local_absmax, fabsf(val));
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}
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local_absmax = GroupReduceMax<THREADS_PER_SUBWARP>(local_absmax);
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float y_scale, y_scale_inv;
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calculate_fp8_scales<SCALE_UE8M0, dst_dtype_info>(local_absmax, y_scale, y_scale_inv);
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float2 y_scale_repeated = {y_scale, y_scale};
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if (lane_id == 0) {
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*scale_output = extract_required_scale_format<SCALE_UE8M0>(y_scale_inv);
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}
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int4 output_buf;
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if constexpr (std::is_same_v<DST_DTYPE, fp8_e4m3_t>) {
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const auto output_buf_ptr = reinterpret_cast<__nv_fp8x2_storage_t*>(&output_buf);
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#pragma unroll
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for (uint32_t j = 0; j < INPUT_PRIMARY_VEC_SIZE; j += 2) {
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float2 inputx2 = {static_cast<float>(input_primary_vec[j]), static_cast<float>(input_primary_vec[j + 1])};
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float2 outputx2 = fmul2_rn(inputx2, y_scale_repeated);
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outputx2.x = fminf(fmaxf(outputx2.x, dst_dtype_info::MIN), dst_dtype_info::MAX);
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outputx2.y = fminf(fmaxf(outputx2.y, dst_dtype_info::MIN), dst_dtype_info::MAX);
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output_buf_ptr[j / 2] = __nv_cvt_float2_to_fp8x2(outputx2, __NV_SATFINITE, __NV_E4M3);
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}
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} else {
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const auto output_buf_ptr = reinterpret_cast<DST_DTYPE*>(&output_buf);
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#pragma unroll
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for (uint32_t j = 0; j < INPUT_PRIMARY_VEC_SIZE; ++j) {
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float val = static_cast<float>(input_primary_vec[j]);
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float q_val = fminf(fmaxf(val * y_scale, dst_dtype_info::MIN), dst_dtype_info::MAX);
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output_buf_ptr[j] = DST_DTYPE(q_val);
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}
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}
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// Ordinary 128-bit vectorized store (STG.128); no inline asm.
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*reinterpret_cast<int4*>(output_q + offset_num_groups * GROUP_SIZE + lane_id * INPUT_PRIMARY_VEC_SIZE) =
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output_buf;
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});
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device::PDLTriggerSecondary<kUsePDL>();
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}
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// ----------------------------------------------------------------------------
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// Launcher (JIT). All shape-derived scalars are computed in the Python wrapper
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// and passed in, so the C++ side only needs TensorView::data_ptr()/device().
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// Runtime combos (column_major / ue8m0 / silu / masked / group_size) are
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// dispatched to the templated kernel; launch is PDL-aware via LaunchKernel.
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// ----------------------------------------------------------------------------
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template <typename S>
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struct TypeTag {
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using type = S;
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};
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template <typename T, typename DST_DTYPE, bool kUsePDL>
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struct PerTokenGroupQuant8bitV2Kernel {
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template <
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typename SCHEDULER,
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int GROUP_SIZE,
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int THREADS_PER_SUBWARP,
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bool IS_COLUMN_MAJOR,
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bool SCALE_UE8M0,
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bool FUSE_SILU_AND_MUL>
|
||||
static void launch(
|
||||
const DLDevice& device,
|
||||
dim3 grid,
|
||||
dim3 block,
|
||||
int subwarps_per_block,
|
||||
int hidden_dim_num_groups,
|
||||
int scale_expert_stride,
|
||||
int scale_hidden_stride,
|
||||
int num_tokens_per_expert,
|
||||
const void* input,
|
||||
void* output_q,
|
||||
void* output_s,
|
||||
const int32_t* masked_m) {
|
||||
using scale_packed_t = std::conditional_t<SCALE_UE8M0, uint32_t, float>;
|
||||
auto kernel = per_token_group_quant_8bit_v2_kernel<
|
||||
SCHEDULER,
|
||||
GROUP_SIZE,
|
||||
THREADS_PER_SUBWARP,
|
||||
T,
|
||||
DST_DTYPE,
|
||||
IS_COLUMN_MAJOR,
|
||||
SCALE_UE8M0,
|
||||
FUSE_SILU_AND_MUL,
|
||||
kUsePDL>;
|
||||
host::LaunchKernel(grid, block, device)
|
||||
.enable_pdl(kUsePDL)(
|
||||
kernel,
|
||||
static_cast<const T*>(input),
|
||||
static_cast<DST_DTYPE*>(output_q),
|
||||
static_cast<scale_packed_t*>(output_s),
|
||||
masked_m,
|
||||
subwarps_per_block,
|
||||
hidden_dim_num_groups,
|
||||
scale_expert_stride,
|
||||
scale_hidden_stride,
|
||||
num_tokens_per_expert);
|
||||
}
|
||||
|
||||
template <int GROUP_SIZE>
|
||||
static void dispatch_bools(
|
||||
const DLDevice& device,
|
||||
bool is_column_major,
|
||||
bool scale_ue8m0,
|
||||
bool fuse_silu_and_mul,
|
||||
bool masked_layout,
|
||||
int num_local_experts,
|
||||
int hidden_dim_num_groups,
|
||||
int num_groups,
|
||||
int scale_expert_stride,
|
||||
int scale_hidden_stride,
|
||||
int num_tokens_per_expert,
|
||||
const void* input,
|
||||
void* output_q,
|
||||
void* output_s,
|
||||
const int32_t* masked_m) {
|
||||
constexpr int THREADS_PER_SUBWARP = GROUP_SIZE / 16;
|
||||
|
||||
auto launch_with_config = [&](auto sched_tag, auto colmajor_tag, auto ue8m0_tag, auto silu_tag) {
|
||||
using SCHEDULER = typename decltype(sched_tag)::type;
|
||||
int subwarps_per_block;
|
||||
dim3 grid, block;
|
||||
SCHEDULER::compute_exec_config(
|
||||
THREADS_PER_SUBWARP, num_local_experts, hidden_dim_num_groups, num_groups, subwarps_per_block, grid, block);
|
||||
launch<
|
||||
SCHEDULER,
|
||||
GROUP_SIZE,
|
||||
THREADS_PER_SUBWARP,
|
||||
decltype(colmajor_tag)::value,
|
||||
decltype(ue8m0_tag)::value,
|
||||
decltype(silu_tag)::value>(
|
||||
device,
|
||||
grid,
|
||||
block,
|
||||
subwarps_per_block,
|
||||
hidden_dim_num_groups,
|
||||
scale_expert_stride,
|
||||
scale_hidden_stride,
|
||||
num_tokens_per_expert,
|
||||
input,
|
||||
output_q,
|
||||
output_s,
|
||||
masked_m);
|
||||
};
|
||||
|
||||
if (is_column_major) {
|
||||
if (scale_ue8m0) {
|
||||
if (fuse_silu_and_mul) {
|
||||
if (masked_layout)
|
||||
launch_with_config(TypeTag<MaskedLayoutScheduler>{}, std::true_type{}, std::true_type{}, std::true_type{});
|
||||
else
|
||||
launch_with_config(TypeTag<NaiveScheduler>{}, std::true_type{}, std::true_type{}, std::true_type{});
|
||||
} else {
|
||||
launch_with_config(TypeTag<NaiveScheduler>{}, std::true_type{}, std::true_type{}, std::false_type{});
|
||||
}
|
||||
} else {
|
||||
launch_with_config(TypeTag<NaiveScheduler>{}, std::true_type{}, std::false_type{}, std::false_type{});
|
||||
}
|
||||
} else {
|
||||
launch_with_config(TypeTag<NaiveScheduler>{}, std::false_type{}, std::false_type{}, std::false_type{});
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
run(tvm::ffi::TensorView input,
|
||||
tvm::ffi::TensorView output_q,
|
||||
tvm::ffi::TensorView output_s,
|
||||
tvm::ffi::TensorView masked_m,
|
||||
int64_t group_size,
|
||||
bool scale_ue8m0,
|
||||
bool fuse_silu_and_mul,
|
||||
bool masked_layout,
|
||||
int64_t num_groups,
|
||||
int64_t num_local_experts,
|
||||
bool is_column_major,
|
||||
int64_t hidden_dim_num_groups,
|
||||
int64_t num_tokens_per_expert,
|
||||
int64_t scale_expert_stride,
|
||||
int64_t scale_hidden_stride) {
|
||||
const DLDevice dev = input.device();
|
||||
const void* in = input.data_ptr();
|
||||
void* oq = output_q.data_ptr();
|
||||
void* os = output_s.data_ptr();
|
||||
const int32_t* masked_ptr = masked_layout ? static_cast<const int32_t*>(masked_m.data_ptr()) : nullptr;
|
||||
|
||||
auto dispatch_gs = [&](auto gs_tag) {
|
||||
constexpr int GS = decltype(gs_tag)::value;
|
||||
static_assert((GS / 16) * INPUT_PRIMARY_VEC_NUM_BYTES == GS * static_cast<int>(sizeof(T)));
|
||||
dispatch_bools<GS>(
|
||||
dev,
|
||||
is_column_major,
|
||||
scale_ue8m0,
|
||||
fuse_silu_and_mul,
|
||||
masked_layout,
|
||||
static_cast<int>(num_local_experts),
|
||||
static_cast<int>(hidden_dim_num_groups),
|
||||
static_cast<int>(num_groups),
|
||||
static_cast<int>(scale_expert_stride),
|
||||
static_cast<int>(scale_hidden_stride),
|
||||
static_cast<int>(num_tokens_per_expert),
|
||||
in,
|
||||
oq,
|
||||
os,
|
||||
masked_ptr);
|
||||
};
|
||||
switch (group_size) {
|
||||
case 16:
|
||||
dispatch_gs(std::integral_constant<int, 16>{});
|
||||
break;
|
||||
case 32:
|
||||
dispatch_gs(std::integral_constant<int, 32>{});
|
||||
break;
|
||||
case 64:
|
||||
dispatch_gs(std::integral_constant<int, 64>{});
|
||||
break;
|
||||
case 128:
|
||||
dispatch_gs(std::integral_constant<int, 128>{});
|
||||
break;
|
||||
default:
|
||||
host::Panic("Unsupported group_size ", group_size);
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
} // namespace
|
||||
@@ -0,0 +1,130 @@
|
||||
from __future__ import annotations
|
||||
|
||||
from typing import TYPE_CHECKING, Optional
|
||||
|
||||
import torch
|
||||
|
||||
from sglang.jit_kernel.utils import (
|
||||
cache_once,
|
||||
is_arch_support_pdl,
|
||||
load_jit,
|
||||
make_cpp_args,
|
||||
)
|
||||
from sglang.kernel_api_logging import debug_kernel_api
|
||||
from sglang.srt.utils.custom_op import register_custom_op
|
||||
|
||||
if TYPE_CHECKING:
|
||||
from tvm_ffi.module import Module
|
||||
|
||||
|
||||
@cache_once
|
||||
def _jit_module(in_dtype: torch.dtype, out_dtype: torch.dtype, use_pdl: bool) -> Module:
|
||||
args = make_cpp_args(in_dtype, out_dtype, use_pdl)
|
||||
return load_jit(
|
||||
"per_token_group_quant_8bit_v2",
|
||||
*args,
|
||||
cuda_files=["gemm/per_token_group_quant_8bit_v2.cuh"],
|
||||
cuda_wrappers=[
|
||||
(
|
||||
"per_token_group_quant_8bit_v2",
|
||||
f"PerTokenGroupQuant8bitV2Kernel<{args}>::run",
|
||||
)
|
||||
],
|
||||
# Match the AOT sgl-kernel build (-use_fast_math) so the FP8 scale
|
||||
# division/rounding is bit-identical to sgl_per_token_group_quant_8bit_v2.
|
||||
extra_cuda_cflags=["--use_fast_math"],
|
||||
)
|
||||
|
||||
|
||||
@register_custom_op(
|
||||
op_name="per_token_group_quant_8bit_v2",
|
||||
mutates_args=["output_q", "output_s"],
|
||||
)
|
||||
def _per_token_group_quant_8bit_v2_custom_op(
|
||||
input: torch.Tensor,
|
||||
output_q: torch.Tensor,
|
||||
output_s: torch.Tensor,
|
||||
group_size: int,
|
||||
eps: float,
|
||||
min_8bit: float,
|
||||
max_8bit: float,
|
||||
scale_ue8m0: bool = False,
|
||||
fuse_silu_and_mul: bool = False,
|
||||
masked_m: Optional[torch.Tensor] = None,
|
||||
) -> None:
|
||||
"""Opaque custom-op boundary around the JIT v2 kernel.
|
||||
|
||||
Registering this as a custom op (instead of calling the tvm-ffi module
|
||||
directly) keeps torch.compile / piecewise-CUDA-graph from tracing into the
|
||||
tvm-ffi ``Function.__call__`` (which Dynamo cannot trace). All shape-derived
|
||||
scalars are computed here and passed to the kernel.
|
||||
|
||||
Layouts (matching the AOT v2):
|
||||
vanilla: input (num_tokens, hidden), output_q (num_tokens, hidden)
|
||||
fuse_silu_and_mul: input (num_tokens, hidden*2), output_q (num_tokens, hidden)
|
||||
fuse_silu_and_mul+masked: input (num_experts, tokens_pad, hidden*2),
|
||||
output_q (num_experts, tokens_pad, hidden), masked_m (num_experts,)
|
||||
"""
|
||||
masked_layout = masked_m is not None
|
||||
numel = input.numel()
|
||||
num_groups = numel // group_size // (2 if fuse_silu_and_mul else 1)
|
||||
if num_groups == 0: # empty input -> grid 0 -> cudaErrorInvalidConfiguration
|
||||
return
|
||||
num_local_experts = input.shape[0] if masked_layout else 1
|
||||
last = output_q.dim() - 1
|
||||
is_column_major = output_s.stride(last - 1) < output_s.stride(last)
|
||||
hidden_dim_num_groups = output_q.shape[last] // group_size
|
||||
num_tokens_per_expert = output_q.shape[last - 1]
|
||||
scale_expert_stride = output_s.stride(0) if masked_layout else 0
|
||||
scale_hidden_stride = output_s.stride(last)
|
||||
|
||||
module = _jit_module(input.dtype, output_q.dtype, is_arch_support_pdl())
|
||||
module.per_token_group_quant_8bit_v2(
|
||||
input,
|
||||
output_q,
|
||||
output_s,
|
||||
masked_m if masked_layout else input, # unused (nullptr) when not masked
|
||||
int(group_size),
|
||||
bool(scale_ue8m0),
|
||||
bool(fuse_silu_and_mul),
|
||||
bool(masked_layout),
|
||||
int(num_groups),
|
||||
int(num_local_experts),
|
||||
bool(is_column_major),
|
||||
int(hidden_dim_num_groups),
|
||||
int(num_tokens_per_expert),
|
||||
int(scale_expert_stride),
|
||||
int(scale_hidden_stride),
|
||||
)
|
||||
|
||||
|
||||
@debug_kernel_api
|
||||
def per_token_group_quant_8bit_v2(
|
||||
input: torch.Tensor,
|
||||
output_q: torch.Tensor,
|
||||
output_s: torch.Tensor,
|
||||
group_size: int,
|
||||
eps: float,
|
||||
min_8bit: float,
|
||||
max_8bit: float,
|
||||
scale_ue8m0: bool = False,
|
||||
fuse_silu_and_mul: bool = False,
|
||||
masked_m: Optional[torch.Tensor] = None,
|
||||
) -> None:
|
||||
"""JIT port of sgl_per_token_group_quant_8bit_v2 (full feature parity).
|
||||
|
||||
Wraps the registered custom op so torch.compile / piecewise CUDA graph treat
|
||||
the tvm-ffi kernel call as an opaque boundary.
|
||||
"""
|
||||
_per_token_group_quant_8bit_v2_custom_op(
|
||||
input=input,
|
||||
output_q=output_q,
|
||||
output_s=output_s,
|
||||
group_size=group_size,
|
||||
eps=eps,
|
||||
min_8bit=min_8bit,
|
||||
max_8bit=max_8bit,
|
||||
scale_ue8m0=scale_ue8m0,
|
||||
fuse_silu_and_mul=fuse_silu_and_mul,
|
||||
masked_m=masked_m,
|
||||
)
|
||||
@@ -73,6 +73,9 @@ if _is_cuda or _is_musa:
|
||||
from sglang.jit_kernel.per_token_group_quant_8bit import (
|
||||
per_token_group_quant_8bit as sgl_per_token_group_quant_8bit_jit,
|
||||
)
|
||||
from sglang.jit_kernel.per_token_group_quant_8bit_v2 import (
|
||||
per_token_group_quant_8bit_v2 as sgl_per_token_group_quant_8bit_jit_v2,
|
||||
)
|
||||
|
||||
if _is_hip:
|
||||
_has_vllm = False
|
||||
@@ -531,7 +534,10 @@ def sglang_per_token_group_quant_fp8(
|
||||
if x.shape[0] > 0:
|
||||
# Temporary
|
||||
if enable_sgl_per_token_group_quant_8bit:
|
||||
if enable_v2:
|
||||
if enable_v2 and _is_musa:
|
||||
# The JIT v2 .cuh uses CUDA-only inline PTX (ld/st.global.v4) and
|
||||
# has no MUSA fallback, so keep MUSA on the AOT v2 op, which
|
||||
# carries the USE_MUSA vector load/store fallbacks.
|
||||
sgl_per_token_group_quant_8bit(
|
||||
x,
|
||||
x_q,
|
||||
@@ -545,6 +551,19 @@ def sglang_per_token_group_quant_fp8(
|
||||
masked_m,
|
||||
enable_v2=True,
|
||||
)
|
||||
elif enable_v2:
|
||||
sgl_per_token_group_quant_8bit_jit_v2(
|
||||
x,
|
||||
x_q,
|
||||
x_s,
|
||||
group_size,
|
||||
eps,
|
||||
fp8_min,
|
||||
fp8_max,
|
||||
scale_ue8m0=scale_ue8m0,
|
||||
fuse_silu_and_mul=fuse_silu_and_mul,
|
||||
masked_m=masked_m,
|
||||
)
|
||||
else:
|
||||
sgl_per_token_group_quant_8bit_jit(
|
||||
input=x,
|
||||
|
||||
Reference in New Issue
Block a user