[AMD] Enable block-fp8 + quick INT4 all-reduce in MiniMax-M3 MI35x nightly Test (#33402)

test/registered/amd/accuracy/mi35x/test_minimax_m3_tp4_eval_mi35x.py

@@ -72,12 +72,17 @@ class ModelConfig:
 
 
 MI35X_MINIMAX_M3_TP4_MODELS = [
+    # MXFP8 + aiter attn + fp8 KV, with the block-fp8 linear path (PR #32036)
+    # and custom/quick INT4 all-reduce (PR #32230) opted in. Both are opt-in
+    # via env: on gfx950 block convert is not automatic
+    # (mxfp8_block_convert_required() is False), and the M3 overrides otherwise
+    # force --disable-custom-all-reduce.
     ModelConfig(
         model_path="MiniMaxAI/MiniMax-M3-MXFP8",
         tp_size=4,
         accuracy_threshold=0.95,
         timeout=5400,
-        variant="TP4+MXFP8+aiterAttn+fp8KV",
+        variant="TP4+MXFP8+aiterAttn+fp8KV+blockFP8+quickAR",
         other_args=[
             "--quantization",
             "mxfp8",
@@ -102,6 +107,15 @@ MI35X_MINIMAX_M3_TP4_MODELS = [
             # router GEMM (torch.mm(bf16, bf16, out_dtype=float32)); force the
             # fp32 router path. Also gives more precise expert routing.
             "SGLANG_OPT_USE_BF16_ROUTER_GEMM": "0",
+            # Block-fp8 linear path (PR #32036): convert MXFP8 linear weights to
+            # block-fp8 [128,128] and run them through the tuned block-scale
+            # (bpreshuffle) GEMM on gfx950.
+            "SGLANG_FORCE_MXFP8_BLOCK_CONVERT": "1",
+            # Custom / quick all-reduce (PR #32230): keep custom all-reduce on so
+            # the INT4 quick-reduce path is used for the TP all-reduce.
+            "SGLANG_M3_ALLOW_CUSTOM_AR": "1",
+            "ROCM_QUICK_REDUCE_QUANTIZATION": "INT4",
+            "ROCM_QUICK_REDUCE_CAST_BF16_TO_FP16": "1",
         },
     ),
 ]