[CI] Rename basic CI stage-a/b/c -> base-a/b/c for symmetry with extra CI (#25420)

2026-05-15 18:26:55 -07:00
parent d0c38329b2
commit b7d62bd724
473 changed files with 745 additions and 746 deletions
@@ -13,7 +13,7 @@ from sglang.test.test_utils import (
    popen_launch_server,
 )

-register_cuda_ci(est_time=160, stage="stage-b", runner_config="1-gpu-large")
+register_cuda_ci(est_time=160, stage="base-b", runner_config="1-gpu-large")
 register_amd_ci(est_time=200, suite="stage-b-test-1-gpu-large-amd")


@@ -10,7 +10,7 @@ from sglang.srt.server_args import ServerArgs, set_global_server_args_for_schedu
 from sglang.test.ci.ci_register import register_amd_ci, register_cuda_ci
 from sglang.test.test_utils import CustomTestCase

-register_cuda_ci(est_time=44, stage="stage-b", runner_config="1-gpu-small")
+register_cuda_ci(est_time=44, stage="base-b", runner_config="1-gpu-small")
 register_amd_ci(est_time=22, suite="stage-b-test-1-gpu-small-amd")


@@ -17,7 +17,7 @@ from sglang.test.test_utils import (

 register_cuda_ci(
    est_time=690,
-    stage="stage-c",
+    stage="base-c",
    runner_config="4-gpu-b200",
 )

@@ -15,7 +15,7 @@ from sglang.test.test_utils import (
 # Per-commit: SymmetricMemory variant only.
 # - TestDeepseekV3FP4 (TRTLLM) archived to test/manual/quant/test_deepseek_v3_fp4_4gpu_trtllm.py
 # - TestDeepseekV3FP4CutlassMoE moved to test_deepseek_v3_fp4_4gpu_extra.py
-register_cuda_ci(est_time=960, stage="stage-c", runner_config="4-gpu-b200")
+register_cuda_ci(est_time=960, stage="base-c", runner_config="4-gpu-b200")

 FULL_DEEPSEEK_V3_FP4_MODEL_PATH = "nvidia/DeepSeek-V3-0324-FP4"
 SERVER_LAUNCH_TIMEOUT = 1200
@@ -9,7 +9,7 @@ from sglang.srt.layers.quantization.fp8_kernel import (
 from sglang.test.ci.ci_register import register_cuda_ci
 from sglang.test.test_utils import CustomTestCase

-register_cuda_ci(est_time=10, stage="stage-b", runner_config="1-gpu-large")
+register_cuda_ci(est_time=10, stage="base-b", runner_config="1-gpu-large")

 from sglang.srt.utils import get_device, is_cuda, is_xpu

@@ -10,7 +10,7 @@ from sglang.srt.layers.quantization.fp8_utils import (
 from sglang.test.ci.ci_register import register_cuda_ci
 from sglang.test.test_utils import CustomTestCase

-register_cuda_ci(est_time=9, stage="stage-b", runner_config="1-gpu-large")
+register_cuda_ci(est_time=9, stage="base-b", runner_config="1-gpu-large")


 class TestInverseTransformScaleUe8m0(CustomTestCase):
@@ -6,7 +6,7 @@ import sglang as sgl
 from sglang.test.ci.ci_register import register_cuda_ci
 from sglang.test.test_utils import CustomTestCase

-register_cuda_ci(est_time=76, stage="stage-b", runner_config="1-gpu-small")
+register_cuda_ci(est_time=76, stage="base-b", runner_config="1-gpu-small")


 class TestGGUF(CustomTestCase):
@@ -11,7 +11,7 @@ from sglang.srt.server_args import ServerArgs, set_global_server_args_for_schedu
 from sglang.test.ci.ci_register import register_cuda_ci
 from sglang.test.test_utils import CustomTestCase

-register_cuda_ci(est_time=15, stage="stage-b", runner_config="1-gpu-small")
+register_cuda_ci(est_time=15, stage="base-b", runner_config="1-gpu-small")


 def native_w8a8_per_token_matmul(A, B, As, Bs, output_dtype=torch.float16):
@@ -4,7 +4,7 @@ from sglang.srt.layers.quantization.utils import is_layer_skipped
 from sglang.test.ci.ci_register import register_cpu_ci
 from sglang.test.test_utils import CustomTestCase

-register_cpu_ci(est_time=5, suite="stage-a-test-cpu")
+register_cpu_ci(est_time=5, suite="base-a-test-cpu")


 # Qwen3-Next FP8 actually publishes the equivalent of this in
@@ -12,7 +12,7 @@ from sglang.test.ci.ci_register import register_cuda_ci
 from sglang.test.test_marlin_utils import awq_marlin_quantize, marlin_quantize
 from sglang.test.test_utils import CustomTestCase

-register_cuda_ci(est_time=108, stage="stage-b", runner_config="1-gpu-small")
+register_cuda_ci(est_time=108, stage="base-b", runner_config="1-gpu-small")

 set_global_server_args_for_scheduler(object.__new__(ServerArgs))

@@ -12,7 +12,7 @@ from sglang.test.test_utils import (
    popen_launch_server,
 )

-register_cuda_ci(est_time=62, stage="stage-b", runner_config="1-gpu-large")
+register_cuda_ci(est_time=62, stage="base-b", runner_config="1-gpu-large")


 class TestModeloptFP8(CustomTestCase):
@@ -12,7 +12,7 @@ from sglang.test.test_utils import (
    try_cached_model,
 )

-register_cuda_ci(est_time=350, stage="stage-c", runner_config="4-gpu-b200")
+register_cuda_ci(est_time=350, stage="base-c", runner_config="4-gpu-b200")

 MODEL_PATH = "nvidia/Llama-3.1-8B-Instruct-NVFP4"

@@ -12,7 +12,7 @@ from sglang.test.test_utils import (
    try_cached_model,
 )

-register_cuda_ci(est_time=109, stage="stage-b", runner_config="1-gpu-small")
+register_cuda_ci(est_time=109, stage="base-b", runner_config="1-gpu-small")

 MODEL_PATH = "nvidia/Llama-3.1-8B-Instruct-NVFP4"

@@ -5,7 +5,7 @@ from sglang.srt.configs.model_config import ModelConfig
 from sglang.test.ci.ci_register import register_cpu_ci
 from sglang.test.test_utils import CustomTestCase

-register_cpu_ci(est_time=15, suite="stage-a-test-cpu")
+register_cpu_ci(est_time=15, suite="base-a-test-cpu")


 class TestQuantLogString(CustomTestCase):
@@ -9,7 +9,7 @@ from sglang.srt.utils.common import get_device
 from sglang.test.ci.ci_register import register_amd_ci, register_cuda_ci
 from sglang.test.test_utils import CustomTestCase

-register_cuda_ci(est_time=11, stage="stage-b", runner_config="1-gpu-small")
+register_cuda_ci(est_time=11, stage="base-b", runner_config="1-gpu-small")
 register_amd_ci(est_time=12, suite="stage-b-test-1-gpu-small-amd")