[Apple Silicon] [CI] Move the MLX lane to the check-changes + pr-gate composite (#30121)

python/sglang/test/ci/ci_register.py

@@ -16,6 +16,7 @@ __all__ = [
     "register_npu_ci",
     "register_xpu_ci",
     "register_musa_ci",
+    "register_mlx_ci",
     "ut_parse_one_file",
 ]
 
@@ -35,6 +36,7 @@ class HWBackend(Enum):
     NPU = auto()
     XPU = auto()
     MUSA = auto()
+    MLX = auto()
 
 
 @dataclass
@@ -148,6 +150,19 @@ def register_musa_ci(
     return None
 
 
+def register_mlx_ci(
+    est_time: float,
+    suite: Optional[str] = None,
+    nightly: bool = False,
+    disabled: Optional[str] = None,
+    *,
+    stage: Optional[str] = None,
+    runner_config: Optional[str] = None,
+):
+    """Marker for MLX CI registration (parsed via AST; runtime no-op)."""
+    return None
+
+
 REGISTER_MAPPING = {
     "register_cpu_ci": HWBackend.CPU,
     "register_cuda_ci": HWBackend.CUDA,
@@ -156,6 +171,7 @@ REGISTER_MAPPING = {
     "register_npu_ci": HWBackend.NPU,
     "register_xpu_ci": HWBackend.XPU,
     "register_musa_ci": HWBackend.MUSA,
+    "register_mlx_ci": HWBackend.MLX,
 }