[CPU][CI]: rename Xeon CPU CI suites to stage-*-intel (#37395)

Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
This commit is contained in:
jundu
2026-09-04 10:08:41 +08:00
committed by GitHub
co-authored by Ma Mingfei
parent c1b4d535d7
commit 8770c1db1f
109 changed files with 115 additions and 115 deletions
+1 -1
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@@ -11,7 +11,7 @@ from sglang.srt.utils.log_utils import create_log_targets, log_json
from sglang.test.ci.ci_register import register_cpu_ci
register_cpu_ci(est_time=6, suite="base-a-test-cpu")
register_cpu_ci(est_time=4, suite="base-c-test-cpu")
register_cpu_ci(est_time=4, suite="stage-b-test-cpu-intel")
_LOG_PREFIX_RE = re.compile(r"^\[\d{4}-\d{2}-\d{2} \d{2}:\d{2}:\d{2}\] ")
@@ -7,7 +7,7 @@ from sglang.srt.utils.network import NetworkAddress, is_zmq_endpoint_ipv6
from sglang.test.ci.ci_register import register_cpu_ci
register_cpu_ci(est_time=7, suite="base-a-test-cpu")
register_cpu_ci(est_time=5, suite="base-c-test-cpu")
register_cpu_ci(est_time=5, suite="stage-b-test-cpu-intel")
# Mock get_device() so ServerArgs tests run on CPU-only CI runners
_mock_device = patch(
+1 -1
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@@ -16,7 +16,7 @@ from sglang.test.test_utils import CustomTestCase
from sglang.utils import normalize_base_url, release_port, reserve_port
register_cpu_ci(est_time=7, suite="base-a-test-cpu")
register_cpu_ci(est_time=8, suite="base-c-test-cpu")
register_cpu_ci(est_time=8, suite="stage-b-test-cpu-intel")
class TestTryBindSocket(CustomTestCase):
@@ -12,7 +12,7 @@ from sglang.test.ci.ci_register import register_amd_ci, register_cpu_ci
from sglang.utils import TypeBasedDispatcher
register_amd_ci(est_time=10, suite="stage-b-test-1-gpu-small-amd")
register_cpu_ci(est_time=6, suite="base-c-test-cpu")
register_cpu_ci(est_time=6, suite="stage-b-test-cpu-intel")
class TestTypeBasedDispatcher(unittest.TestCase):