minke.yu/sglang
1
0
Fork 0
Code Issues Pull Requests Actions 12 Packages Projects Releases Wiki Activity

docs(semianalysis): Update Qwen3.5 B200 NVFP4 MTP config (#34357)

Browse Source
This commit is contained in:
Faradawn Yang
2026-08-11 16:12:17 -07:00
committed by GitHub
parent d82a1d4802
commit 857910bd35
2 changed files with 8 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files
docs/cookbook/autoregressive/Qwen/Qwen3.5.mdx
+2 -2
View File
@@ -157,7 +157,7 @@ This section provides deployment configurations optimized for different hardware
- **MI325X (256GB)** runs with tp=2. - **MI325X (256GB)** runs with tp=2.
- **MI355X (288GB)** runs with tp=2. - **MI355X (288GB)** runs with tp=2.
- **FP4**: The FP4 quantized model requires ~250GB for weights, cutting memory by almost 4x. NVFP4 ([nvidia/Qwen3.5-397B-A17B-NVFP4-V2](https://huggingface.co/nvidia/Qwen3.5-397B-A17B-NVFP4-V2)) requires B200/B300 (Blackwell architecture); AMD provides an MXFP4 checkpoint ([amd/Qwen3.5-397B-A17B-MXFP4](https://huggingface.co/amd/Qwen3.5-397B-A17B-MXFP4)) for MI355X. - **FP4**: The FP4 quantized model requires ~250GB for weights, cutting memory by almost 4x. NVFP4 ([nvidia/Qwen3.5-397B-A17B-NVFP4-V2](https://huggingface.co/nvidia/Qwen3.5-397B-A17B-NVFP4-V2)) requires B200/B300 (Blackwell architecture); AMD provides an MXFP4 checkpoint ([amd/Qwen3.5-397B-A17B-MXFP4](https://huggingface.co/amd/Qwen3.5-397B-A17B-MXFP4)) for MI355X.
- **B200 (183GB)** runs with tp=4. (NVFP4) - **B200 (183GB)** runs with tp=4 (tp=2 with expert parallelism 2 when MTP is enabled). (NVFP4)
- **B300 (275GB)** runs with tp=2. (NVFP4) - **B300 (275GB)** runs with tp=2. (NVFP4)
- **MI355X (288GB)** runs with tp=2 (use tp=4 for low concurrency). (MXFP4) - **MI355X (288GB)** runs with tp=2 (use tp=4 for low concurrency). (MXFP4)
@@ -191,7 +191,7 @@ This section provides deployment configurations optimized for different hardware
<td style={{padding: "9px 12px", backgroundColor: "rgba(255,255,255,0.05)"}}>183GB</td> <td style={{padding: "9px 12px", backgroundColor: "rgba(255,255,255,0.05)"}}>183GB</td>
<td style={{padding: "9px 12px", backgroundColor: "rgba(255,255,255,0.02)"}}>8</td> <td style={{padding: "9px 12px", backgroundColor: "rgba(255,255,255,0.02)"}}>8</td>
<td style={{padding: "9px 12px", backgroundColor: "rgba(255,255,255,0.05)"}}>4</td> <td style={{padding: "9px 12px", backgroundColor: "rgba(255,255,255,0.05)"}}>4</td>
<td style={{padding: "9px 12px", backgroundColor: "rgba(255,255,255,0.02)"}}>4</td> <td style={{padding: "9px 12px", backgroundColor: "rgba(255,255,255,0.02)"}}>4 / 2 + EP2 (MTP)</td>
</tr> </tr>
<tr> <tr>
<td style={{padding: "9px 12px", fontWeight: 500, backgroundColor: "rgba(255,255,255,0.02)"}}>B300</td> <td style={{padding: "9px 12px", fontWeight: 500, backgroundColor: "rgba(255,255,255,0.02)"}}>B300</td>
docs/src/snippets/autoregressive/qwen35-deployment.jsx
+6 -1
View File
@@ -20,7 +20,7 @@ export const Qwen35Deployment = () => {
// 35B-A3B: H100 tp=1, H200 tp=1, B200 tp=1, B300 tp=1, MI300X tp=1, MI325X tp=1, MI355X tp=1 // 35B-A3B: H100 tp=1, H200 tp=1, B200 tp=1, B300 tp=1, MI300X tp=1, MI325X tp=1, MI355X tp=1
// 27B: tp=1 on all hardware (including MI300X, MI325X, MI355X) // 27B: tp=1 on all hardware (including MI300X, MI325X, MI355X)
// //
// FP4 (397B only): NVFP4 on Blackwell B200/B300 tp=4; AMD MXFP4 on MI355X tp=2 // FP4 (397B only): NVFP4 on Blackwell B200 tp=4 (tp=2 ep=2 w/ MTP) / B300 tp=4; AMD MXFP4 on MI355X tp=2
const MOE_MODELS = new Set(['397b', '122b', '35b']); const MOE_MODELS = new Set(['397b', '122b', '35b']);
const FP8_MODELS = new Set(['397b', '122b', '35b', '27b']); const FP8_MODELS = new Set(['397b', '122b', '35b', '27b']);
@@ -315,6 +315,11 @@ export const Qwen35Deployment = () => {
if (model === '122b' && hardware === 'h100' && quantization === 'fp8' && speculative === 'enabled') { if (model === '122b' && hardware === 'h100' && quantization === 'fp8' && speculative === 'enabled') {
hwConfig = { ...hwConfig, tp: 4, mem: undefined }; hwConfig = { ...hwConfig, tp: 4, mem: undefined };
} }
// 397B B200 NVFP4 with MTP: tp=2 with expert parallelism 2 (TEP2) beats
// tp=4 across the concurrency sweep.
if (model === '397b' && hardware === 'b200' && quantization === 'fp4' && speculative === 'enabled') {
hwConfig = { ...hwConfig, tp: 2, ep: 2, mem: 0.8 };
}
let modelName; let modelName;
if (quantization === 'fp4') { if (quantization === 'fp4') {