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[Refactor] Rename NSA → DSA: user-facing aliases, file/class/import rename (#25821)

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Co-authored-by: Claude Sonnet 4.6 (1M context) <noreply@anthropic.com>
This commit is contained in:
Cheng Wan
2026-05-20 00:18:04 -07:00
committed by GitHub
co-authored by Claude Sonnet 4.6
parent da6d549ab2
commit 8131641bc6
162 changed files with 11298 additions and 10740 deletions
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test/manual/dsv4/test_b200_flash.py
+2 -2
View File
@@ -87,8 +87,8 @@ class TestB200FlashCP(DSV4FlashAime25TestBase):
"4",
"--moe-a2a-backend",
"deepep",
"--enable-nsa-prefill-context-parallel",
"--nsa-prefill-cp-mode",
"--enable-dsa-prefill-context-parallel",
"--dsa-prefill-cp-mode",
"round-robin-split",
"--chunked-prefill-size",
"16384",
test/manual/dsv4/test_b200_pro.py
+2 -2
View File
@@ -101,8 +101,8 @@ class TestB200ProCP(DSV4ProAime25TestBase):
"8",
"--moe-a2a-backend",
"deepep",
"--enable-nsa-prefill-context-parallel",
"--nsa-prefill-cp-mode",
"--enable-dsa-prefill-context-parallel",
"--dsa-prefill-cp-mode",
"round-robin-split",
"--chunked-prefill-size",
"16384",
test/manual/dsv4/test_b300_flash.py
+2 -2
View File
@@ -89,8 +89,8 @@ class TestB300FlashCP(DSV4FlashAime25TestBase):
"4",
"--moe-a2a-backend",
"deepep",
"--enable-nsa-prefill-context-parallel",
"--nsa-prefill-cp-mode",
"--enable-dsa-prefill-context-parallel",
"--dsa-prefill-cp-mode",
"round-robin-split",
"--chunked-prefill-size",
"16384",
test/manual/dsv4/test_b300_pro.py
+2 -2
View File
@@ -103,8 +103,8 @@ class TestB300ProCP(DSV4ProAime25TestBase):
"8",
"--moe-a2a-backend",
"deepep",
"--enable-nsa-prefill-context-parallel",
"--nsa-prefill-cp-mode",
"--enable-dsa-prefill-context-parallel",
"--dsa-prefill-cp-mode",
"round-robin-split",
"--chunked-prefill-size",
"16384",
test/manual/dsv4/test_dsv4_pd_disagg_nixl.py
+1 -1
View File
@@ -1,7 +1,7 @@
"""DSV4 Flash PD-disagg with NIXL backend. Both sides run dp-attention
+ deepep + EAGLE MTP so attn_tp_size and the V4 state pool layout are
fully symmetric: same SWA item_len under matching attn_tp, and same
NSA c4/c128 indexer ring buffer size under matching spec status. nixl
DSA c4/c128 indexer ring buffer size under matching spec status. nixl
`send_state` is page-by-index and has no V4 TP-slice / spec-asymmetric
path, so any layout mismatch would trip the item_len assert in
`nixl/conn.py`."""
test/manual/dsv4/test_gb300_flash.py
+2 -2
View File
@@ -87,8 +87,8 @@ class TestGB300FlashCP(DSV4FlashAime25TestBase):
"4",
"--moe-a2a-backend",
"deepep",
"--enable-nsa-prefill-context-parallel",
"--nsa-prefill-cp-mode",
"--enable-dsa-prefill-context-parallel",
"--dsa-prefill-cp-mode",
"round-robin-split",
"--chunked-prefill-size",
"16384",
test/manual/dsv4/test_gb300_pro.py
+2 -2
View File
@@ -103,8 +103,8 @@ class TestGB300ProCP(DSV4ProAime25TestBase):
"4",
"--moe-a2a-backend",
"deepep",
"--enable-nsa-prefill-context-parallel",
"--nsa-prefill-cp-mode",
"--enable-dsa-prefill-context-parallel",
"--dsa-prefill-cp-mode",
"round-robin-split",
"--chunked-prefill-size",
"16384",
test/manual/dsv4/test_h200_fp8_flash.py
+2 -2
View File
@@ -98,8 +98,8 @@ class TestH200Fp8FlashCP(DSV4FlashAime25TestBase):
"4",
"--moe-a2a-backend",
"deepep",
"--enable-nsa-prefill-context-parallel",
"--nsa-prefill-cp-mode",
"--enable-dsa-prefill-context-parallel",
"--dsa-prefill-cp-mode",
"round-robin-split",
"--chunked-prefill-size",
"16384",