[ci] split stage-c-test-4-gpu-b200 to enable a low-disk runner pool (#23417)

Co-authored-by: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
Kangyan-Zhou
2026-04-21 18:33:33 -07:00
committed by GitHub
co-authored by Claude Opus 4.7
parent 6cf0b004ca
commit 77fd86f89e
15 changed files with 84 additions and 14 deletions
@@ -4,7 +4,7 @@ from sglang.test.ci.ci_register import register_cuda_ci
from sglang.test.gpt_oss_common import BaseTestGptOss
register_cuda_ci(est_time=328, suite="stage-c-test-4-gpu-h100")
register_cuda_ci(est_time=740, suite="stage-c-test-4-gpu-b200")
register_cuda_ci(est_time=740, suite="stage-c-test-4-gpu-b200-small")
class TestGptOss4Gpu(BaseTestGptOss):
@@ -11,7 +11,7 @@ from sglang.test.test_utils import (
popen_launch_server,
)
register_cuda_ci(est_time=710, suite="stage-c-test-4-gpu-b200")
register_cuda_ci(est_time=710, suite="nightly-4-gpu-b200", nightly=True)
NEMOTRON_3_SUPER_NVFP4_MODEL = "nvidia/NVIDIA-Nemotron-3-Super-120B-A12B-NVFP4"
@@ -15,7 +15,7 @@ from sglang.test.test_utils import (
popen_launch_server,
)
register_cuda_ci(est_time=540, suite="stage-c-test-4-gpu-b200")
register_cuda_ci(est_time=540, suite="stage-c-test-4-gpu-b200-small")
QWEN35_FP4_MODEL = "nvidia/Qwen3.5-397B-A17B-NVFP4"
ACC_THRESHOLDS = {QWEN35_FP4_MODEL: {"gsm8k": 0.95}}
@@ -11,7 +11,7 @@ from sglang.test.test_utils import (
ModelLaunchSettings,
)
register_cuda_ci(est_time=720, suite="stage-c-test-4-gpu-b200")
register_cuda_ci(est_time=720, suite="stage-c-test-4-gpu-b200-small")
QWEN35_FP4_MODEL = "nvidia/Qwen3.5-397B-A17B-NVFP4"
ACC_THRESHOLDS = {QWEN35_FP4_MODEL: {"gsm8k": 0.95}}
@@ -36,7 +36,7 @@ from sglang.test.test_utils import CustomTestCase
register_cuda_ci(
est_time=300,
suite="stage-c-test-4-gpu-b200",
suite="stage-c-test-4-gpu-b200-small",
)
BASE_MODEL = "lmsys/gpt-oss-20b-bf16"
@@ -36,7 +36,7 @@ from sglang.test.test_utils import CustomTestCase
register_cuda_ci(
est_time=160,
suite="stage-c-test-4-gpu-b200",
suite="stage-c-test-4-gpu-b200-small",
)
BASE_MODEL = "Qwen/Qwen3-30B-A3B-Instruct-2507"
@@ -36,7 +36,7 @@ from sglang.test.test_utils import CustomTestCase
register_cuda_ci(
est_time=160,
suite="stage-c-test-4-gpu-b200",
suite="stage-c-test-4-gpu-b200-small",
)
BASE_MODEL = "Qwen/Qwen3-VL-30B-A3B-Instruct"
+1 -1
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@@ -16,7 +16,7 @@ except ImportError:
CuteDslMoEWrapper = None
convert_sf_to_mma_layout = None
register_cuda_ci(est_time=590, suite="stage-c-test-4-gpu-b200")
register_cuda_ci(est_time=590, suite="stage-c-test-4-gpu-b200-small")
SKIP_TEST = torch.cuda.get_device_capability() < (10, 0)
SKIP_REASON = "Nvfp4 Requires compute capability of 10 or above."
@@ -12,7 +12,7 @@ from sglang.test.test_utils import (
try_cached_model,
)
register_cuda_ci(est_time=630, suite="stage-c-test-4-gpu-b200")
register_cuda_ci(est_time=630, suite="nightly-4-gpu-b200", nightly=True)
MODEL_PATH = "Qwen/Qwen3-4B-Instruct-2507-FP8"
MXFP8_MODEL_PATH = "zianglih/Qwen3-4B-Instruct-2507-MXFP8"
+1 -1
View File
@@ -12,7 +12,7 @@ from sglang.test.test_utils import (
try_cached_model,
)
register_cuda_ci(est_time=550, suite="stage-c-test-4-gpu-b200")
register_cuda_ci(est_time=550, suite="nightly-4-gpu-b200", nightly=True)
MODEL_PATH = "nvidia/Llama-3.1-8B-Instruct-NVFP4"
@@ -1,6 +1,6 @@
from sglang.test.ci.ci_register import register_cuda_ci
register_cuda_ci(est_time=149, suite="stage-c-test-4-gpu-b200")
register_cuda_ci(est_time=149, suite="stage-c-test-4-gpu-b200-small")
import unittest
@@ -17,7 +17,7 @@ from sglang.test.test_utils import (
)
# EAGLE with DP attention on B200 (tp=2, dp=2, requires 4 B200 GPUs)
register_cuda_ci(est_time=136, suite="stage-c-test-4-gpu-b200")
register_cuda_ci(est_time=136, suite="stage-c-test-4-gpu-b200-small")
def test_gsm8k(base_url: str, model: str):
+1
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@@ -48,6 +48,7 @@ PER_COMMIT_SUITES = {
"stage-b-kernel-benchmark-1-gpu-large",
"stage-c-test-4-gpu-h100",
"stage-c-test-4-gpu-b200",
"stage-c-test-4-gpu-b200-small",
"stage-c-test-4-gpu-gb200",
"stage-c-test-8-gpu-h20",
"stage-c-test-8-gpu-h200",