Route concat MLA to JIT and remove unused downcast (#25843)
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@@ -1,106 +0,0 @@
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import torch
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import triton
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import triton.testing
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from sglang.jit_kernel.benchmark.utils import (
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DEFAULT_DEVICE,
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get_benchmark_range,
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run_benchmark,
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)
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from sglang.jit_kernel.cast import downcast_fp8 as downcast_fp8_jit
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from sglang.test.ci.ci_register import register_cuda_ci
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register_cuda_ci(est_time=10, suite="base-b-kernel-benchmark-1-gpu-large")
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DEVICE = DEFAULT_DEVICE
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DTYPE = torch.bfloat16
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# ── Config ranges ──────────────────────────────────────────────────────────────
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SL_LIST = get_benchmark_range(
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full_range=[4, 16, 64, 256, 512, 1024, 2048],
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ci_range=[4, 64],
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)
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HEAD_DIM_LIST = get_benchmark_range(
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full_range=[(8, 128), (32, 128), (8, 256), (32, 256)],
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ci_range=[(8, 128)],
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)
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CONFIGS = [(sl, h, d, sl * 2) for sl in SL_LIST for h, d in HEAD_DIM_LIST]
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LINE_VALS = ["jit"]
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LINE_NAMES = ["JIT (cast.cuh, 256 threads, 2D grid)"]
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STYLES = [("orange", "-")]
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# ── Perf report ────────────────────────────────────────────────────────────────
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@triton.testing.perf_report(
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triton.testing.Benchmark(
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x_names=["input_sl", "head", "dim", "out_sl"],
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x_vals=CONFIGS,
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line_arg="provider",
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line_vals=LINE_VALS,
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line_names=LINE_NAMES,
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styles=STYLES,
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ylabel="us",
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plot_name="downcast-fp8-jit",
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args={},
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)
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)
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def benchmark(input_sl, head, dim, out_sl, provider):
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k = torch.randn(input_sl, head, dim, dtype=DTYPE, device=DEVICE)
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v = torch.randn(input_sl, head, dim, dtype=DTYPE, device=DEVICE)
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k_out = torch.zeros(out_sl, head, dim, dtype=torch.uint8, device=DEVICE)
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v_out = torch.zeros(out_sl, head, dim, dtype=torch.uint8, device=DEVICE)
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k_scale = torch.tensor([1.0], dtype=torch.float32, device=DEVICE)
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v_scale = torch.tensor([1.0], dtype=torch.float32, device=DEVICE)
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loc = torch.arange(input_sl, dtype=torch.int64, device=DEVICE)
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fn = lambda: downcast_fp8_jit(k, v, k_out, v_out, k_scale, v_scale, loc)
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return run_benchmark(fn)
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# ── Bandwidth analysis ─────────────────────────────────────────────────────────
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def _report_bandwidth(input_sl, head, dim, dtype):
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elem_bytes = torch.finfo(dtype).bits // 8
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total_bytes = input_sl * head * dim * (2 * elem_bytes + 2)
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k = torch.randn(input_sl, head, dim, dtype=dtype, device=DEVICE)
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v = torch.randn(input_sl, head, dim, dtype=dtype, device=DEVICE)
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k_out = torch.zeros(input_sl * 2, head, dim, dtype=torch.uint8, device=DEVICE)
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v_out = torch.zeros(input_sl * 2, head, dim, dtype=torch.uint8, device=DEVICE)
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k_scale = torch.tensor([1.0], dtype=torch.float32, device=DEVICE)
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v_scale = torch.tensor([1.0], dtype=torch.float32, device=DEVICE)
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loc = torch.arange(input_sl, dtype=torch.int64, device=DEVICE)
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jit_fn = lambda: downcast_fp8_jit(k, v, k_out, v_out, k_scale, v_scale, loc)
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jit_ms, _, _ = triton.testing.do_bench(jit_fn, quantiles=[0.5, 0.2, 0.8])
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def fmt(ms):
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return f"{ms*1000:6.2f}us {total_bytes/(ms*1e-3)/1e9:6.0f}GB/s"
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print(f" sl={input_sl:5d} h={head:2d} d={dim:4d}" f" | jit {fmt(jit_ms)}")
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def report_bandwidth():
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print(f"\n{'='*95}")
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print(" JIT (cast.cuh, 256 threads, 2D grid)")
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print(f" dtype={DTYPE}, device={DEVICE}")
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print(f"{'='*95}")
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for sl in [64, 256, 1024, 2048]:
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for h, d in [(8, 128), (32, 128), (8, 256), (32, 256)]:
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_report_bandwidth(sl, h, d, DTYPE)
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print()
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if __name__ == "__main__":
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benchmark.run(print_data=True)
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report_bandwidth()
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@@ -1,52 +0,0 @@
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from __future__ import annotations
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from typing import TYPE_CHECKING
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import torch
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from sglang.jit_kernel.utils import cache_once, load_jit, make_cpp_args
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if TYPE_CHECKING:
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from tvm_ffi.module import Module
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@cache_once
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def _jit_cast_module(dtype: torch.dtype) -> Module:
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args = make_cpp_args(dtype)
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return load_jit(
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"cast",
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*args,
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cuda_files=["elementwise/cast.cuh"],
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cuda_wrappers=[("downcast_fp8", f"downcast_fp8<{args}>")],
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)
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def downcast_fp8(
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k: torch.Tensor,
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v: torch.Tensor,
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k_out: torch.Tensor,
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v_out: torch.Tensor,
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k_scale: torch.Tensor,
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v_scale: torch.Tensor,
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loc: torch.Tensor,
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mult: int = 1,
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offset: int = 0,
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) -> None:
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"""Fused downcast of KV cache tensors from bf16/fp16 to fp8 (E4M3).
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Scales each value by the inverse of its per-tensor scale, clamps to the
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fp8 representable range [-448, 448], then converts to fp8 storage.
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Args:
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k: [input_sl, head, dim] bf16/fp16 CUDA tensor
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v: [input_sl, head, dim] bf16/fp16 CUDA tensor
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k_out: [out_sl, head, dim] uint8 CUDA tensor (fp8 storage)
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v_out: [out_sl, head, dim] uint8 CUDA tensor (fp8 storage)
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k_scale: [1] float32 CUDA tensor, scale for k
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v_scale: [1] float32 CUDA tensor, scale for v
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loc: [input_sl] int64 CUDA tensor, destination sequence indices
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mult: stride multiplier for output index (default 1)
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offset: offset added to output index (default 0)
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"""
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module = _jit_cast_module(k.dtype)
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module.downcast_fp8(k, v, k_out, v_out, k_scale, v_scale, loc, mult, offset)
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@@ -1,137 +0,0 @@
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#pragma once
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// Optimized cast kernel: fixed 256 threads, scaled out via 2D grid.
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// Each thread handles exactly one float4 (kVecSize fp16/bf16 elements).
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// No per-thread loop — pure grid scaling for any head*dim.
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#include <sgl_kernel/tensor.h>
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#include <sgl_kernel/utils.h>
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#include <sgl_kernel/type.cuh> // For dtype_trait fp8 specialization
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#include <sgl_kernel/utils.cuh> // For LaunchKernel
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#include <sgl_kernel/vec.cuh> // For AlignedVector
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#include <dlpack/dlpack.h>
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#include <tvm/ffi/container/tensor.h>
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#include <cstdint>
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namespace {
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constexpr int kBlockSize = 256;
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template <typename T>
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__global__ void fused_downcast_kernel(
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const T* __restrict__ cache_k,
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const T* __restrict__ cache_v,
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const float* __restrict__ k_scale,
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const float* __restrict__ v_scale,
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fp8_e4m3_t* __restrict__ output_k,
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fp8_e4m3_t* __restrict__ output_v,
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const int input_num_tokens,
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const int head,
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const int dim,
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const T max_fp8,
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const T min_fp8,
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const int64_t mult,
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const int64_t offset,
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const int64_t* __restrict__ loc) {
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using namespace device;
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constexpr int kVecSize = 16 / sizeof(T);
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using vec_t = AlignedVector<T, kVecSize>;
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using out_vec_t = AlignedVector<fp8_e4m3_t, kVecSize>;
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const int token_idx = blockIdx.x;
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const int vec_idx = blockIdx.y * kBlockSize + threadIdx.x;
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const int num_vecs = head * dim / kVecSize;
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if (token_idx >= input_num_tokens || vec_idx >= num_vecs) return;
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T k_scale_inv = static_cast<T>(1.f) / cast<T>(k_scale[0]);
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T v_scale_inv = static_cast<T>(1.f) / cast<T>(v_scale[0]);
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auto clamp = [&](T val) { return val > max_fp8 ? max_fp8 : (min_fp8 > val ? min_fp8 : val); };
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const int out_seq_idx = loc[token_idx];
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const T* in_k_base = cache_k + token_idx * head * dim;
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const T* in_v_base = cache_v + token_idx * head * dim;
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fp8_e4m3_t* out_k_base = output_k + (out_seq_idx * mult + offset) * head * dim;
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fp8_e4m3_t* out_v_base = output_v + (out_seq_idx * mult + offset) * head * dim;
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vec_t k_vec, v_vec;
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k_vec.load(in_k_base, vec_idx);
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v_vec.load(in_v_base, vec_idx);
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out_vec_t out_k, out_v;
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#pragma unroll
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for (int j = 0; j < kVecSize; j++) {
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out_k[j] = cast<fp8_e4m3_t>(clamp(k_vec[j] * k_scale_inv));
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out_v[j] = cast<fp8_e4m3_t>(clamp(v_vec[j] * v_scale_inv));
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}
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out_k.store(out_k_base, vec_idx);
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out_v.store(out_v_base, vec_idx);
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}
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template <typename T>
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void downcast_fp8(
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tvm::ffi::TensorView k,
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tvm::ffi::TensorView v,
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tvm::ffi::TensorView k_out,
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tvm::ffi::TensorView v_out,
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tvm::ffi::TensorView k_scale,
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tvm::ffi::TensorView v_scale,
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tvm::ffi::TensorView loc,
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int64_t mult,
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int64_t offset) {
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using namespace host;
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auto input_num_tokens = SymbolicSize{"input_num_tokens"};
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auto head = SymbolicSize{"head"};
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auto dim = SymbolicSize{"dim"};
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auto output_num_tokens = SymbolicSize{"out_sl"};
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auto device = SymbolicDevice{};
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device.set_options<kDLCUDA>();
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TensorMatcher({input_num_tokens, head, dim}).with_dtype<T>().with_device(device).verify(k);
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TensorMatcher({input_num_tokens, head, dim}).with_dtype<T>().with_device(device).verify(v);
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TensorMatcher({output_num_tokens, head, dim}).with_dtype<uint8_t>().with_device(device).verify(k_out);
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TensorMatcher({output_num_tokens, head, dim}).with_dtype<uint8_t>().with_device(device).verify(v_out);
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TensorMatcher({1}).with_dtype<float>().with_device(device).verify(k_scale);
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TensorMatcher({1}).with_dtype<float>().with_device(device).verify(v_scale);
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TensorMatcher({input_num_tokens}).with_dtype<int64_t>().with_device(device).verify(loc);
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const int num_tokens = static_cast<int>(input_num_tokens.unwrap());
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const int h = static_cast<int>(head.unwrap());
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const int d = static_cast<int>(dim.unwrap());
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constexpr int kVecSize = 16 / sizeof(T);
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const int num_vecs = h * d / kVecSize;
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const int grid_y = (num_vecs + kBlockSize - 1) / kBlockSize;
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dim3 grid(num_tokens, grid_y);
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dim3 block(kBlockSize);
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const T max_fp8 = static_cast<T>(kFP8E4M3Max);
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const T min_fp8 = static_cast<T>(-kFP8E4M3Max);
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LaunchKernel(grid, block, device.unwrap())(
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fused_downcast_kernel<T>,
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static_cast<const T*>(k.data_ptr()),
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static_cast<const T*>(v.data_ptr()),
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static_cast<const float*>(k_scale.data_ptr()),
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static_cast<const float*>(v_scale.data_ptr()),
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static_cast<fp8_e4m3_t*>(k_out.data_ptr()),
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static_cast<fp8_e4m3_t*>(v_out.data_ptr()),
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num_tokens,
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h,
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d,
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max_fp8,
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min_fp8,
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mult,
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offset,
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static_cast<const int64_t*>(loc.data_ptr()));
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}
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} // namespace
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@@ -10,7 +10,7 @@ FLASHMLA_CREATE_KV_BLOCK_SIZE_TRITON = tl.constexpr(_FLASHMLA_CREATE_KV_BLOCK_SI
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_is_cuda = is_cuda()
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if _is_cuda:
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from sgl_kernel import concat_mla_absorb_q
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from sglang.jit_kernel.concat_mla import concat_mla_absorb_q
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from sglang.jit_kernel.utils import is_arch_support_pdl
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@@ -32,7 +32,11 @@ if TYPE_CHECKING:
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from sglang.srt.models.deepseek_v2 import DeepseekV2AttentionMLA
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if _is_cuda:
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from sgl_kernel import concat_mla_k, merge_state_v2
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from sgl_kernel import merge_state_v2
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from sglang.jit_kernel.concat_mla import concat_mla_k
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elif _is_musa:
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from sgl_kernel import concat_mla_k
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if _use_aiter_gfx95:
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from aiter.ops.triton.fused_fp8_quant import fused_rms_fp8_group_quant
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@@ -79,8 +79,9 @@ _is_cublas_ge_129 = is_nvidia_cublas_version_ge_12_9()
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if _is_cuda:
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try:
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from sgl_kernel import bmm_fp8, concat_mla_k, merge_state_v2
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from sgl_kernel import bmm_fp8, merge_state_v2
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from sglang.jit_kernel.concat_mla import concat_mla_k
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from sglang.srt.layers.quantization.fp8_kernel import per_tensor_quant_mla_fp8
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_has_fp8_support = True
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