[AMD] Enable HiCache for GLM-5.2 MI355X throughput recipe (#40570)
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@@ -124,7 +124,7 @@ import { Playground } from "/src/snippets/_playground.jsx";
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**gfx950 block-FP8 accuracy: fixed as of the pinned MI355X image (`v0.5.13.post1-rocm720-mi35x-20260618`).** Earlier SGLang ROCm images miscompiled AMD aiter's `gemm_a8w8_blockscale_bpreshuffle` GEMM on gfx950 (ROCm 7.2): the error was small per layer but compounded across all 78 layers and silently corrupted output — in-context reasoning broke (GSM8K ≈ 0) while short factual prompts still looked fine. The root cause was a gfx950/ROCm-7.2 miscompile of the CK kernel (a packed illegal-type FMA that relied on an LLVM coercion pass removed in ROCm 7.2; non-deterministic wrong rows near tile boundaries). This is resolved in the pinned image and newer: GLM-5.2-FP8 on MI350X/MI355X (gfx950) was re-validated at TP4 and TP8 — **GSM8K ≈ 0.96 (0% invalid)** and **15/15 needle-in-haystack retrieval to ~118K tokens**. **MI300X / MI325X (gfx942) were never affected.** If you must run an older image, treat gfx950 FP8 output as unverified. Background: [sgl-project/sglang#28685](https://github.com/sgl-project/sglang/issues/28685) (analysis) and the upstream CK fix [ROCm/rocm-libraries#8639](https://github.com/ROCm/rocm-libraries/pull/8639) (scalar FMA + accumulator anchor; restores correctness and determinism at -O3).
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</Note>
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- **MTP / EAGLE speculative decoding on AMD.** Five-step MTP is validated for `amd/GLM-5.2-MXFP4` on MI355X with `lmsysorg/sglang-rocm:v0.5.19-rocm720-mi35x-20260916`. Choose **Low-Latency** for the GPU-resident TP8/EP1 topology, or **High-Throughput** for the TP4/EP4 topology. Both emit `--speculative-num-steps 5 --speculative-eagle-topk 1 --speculative-num-draft-tokens 6` with the Triton DSA prefill and decode backends. The TP4/EP4 InferenceX benchmark adds HiCache DRAM offload, but those host-specific knobs are intentionally omitted from the portable cookbook command. MTP remains unvalidated for GLM-5.2 on MI300X/MI325X and for the other MI355X checkpoint precisions.
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- **MTP / EAGLE speculative decoding on AMD.** Five-step MTP is validated for `amd/GLM-5.2-MXFP4` on MI355X with `lmsysorg/sglang-rocm:v0.5.20-rocm720-mi35x-20260920`. Choose **Low-Latency** for TP8/EP1, or **High-Throughput** for TP4/EP4 with HiCache (`--enable-hierarchical-cache --hicache-ratio 1.0`). HiCache uses the default `kernel`, `page_first`, and `write_through` settings. MTP remains unvalidated for GLM-5.2 on MI300X/MI325X and for the other MI355X checkpoint precisions.
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## 3. Advanced Usage
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@@ -97,7 +97,7 @@ sgl-eval run aime25 \\
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gb300: "lmsysorg/sglang:latest",
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b300: "lmsysorg/sglang:latest",
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mi355x: "lmsysorg/sglang-rocm:v0.5.13.post1-rocm720-mi35x-20260618",
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"mi355x|mxfp4": "lmsysorg/sglang-rocm:v0.5.19-rocm720-mi35x-20260916",
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"mi355x|mxfp4": "lmsysorg/sglang-rocm:v0.5.20-rocm720-mi35x-20260920",
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mi325x: "lmsysorg/sglang-rocm:v0.5.13.post1-rocm700-mi30x-20260616",
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mi300x: "lmsysorg/sglang-rocm:v0.5.13.post1-rocm700-mi30x-20260616",
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},
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@@ -1011,7 +1011,7 @@ sgl-eval run aime25 \\
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// weights fit a 4-GPU slice, mirroring the amd/GLM-5.1-MXFP4 MI355X recipe (same DSA
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// architecture family) — --trust-remote-code (Quark custom quant config)
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// and --kv-cache-dtype fp8_e4m3 both come from that precedent. Pinned to a
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// newer image (v0.5.19, see dockerImages["mi355x|mxfp4"]) than the FP8/BF16
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// newer image (v0.5.20, see dockerImages["mi355x|mxfp4"]) than the FP8/BF16
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// mi355x cells. Low-Latency uses validated TP8/EP1; High-Throughput uses
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// validated TP4/EP4. Both use five-step MTP from InferenceX PR #2900.
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// DSA backend: triton (SGLang's ROCm default).
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@@ -1075,6 +1075,8 @@ sgl-eval run aime25 \\
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"--speculative-num-steps 5",
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"--speculative-eagle-topk 1",
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"--speculative-num-draft-tokens 6",
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"--enable-hierarchical-cache",
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"--hicache-ratio 1.0",
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"--mem-fraction-static 0.85",
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"--cuda-graph-max-bs-decode 256",
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"--max-running-requests 256",
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