chore: update CI test est_time values (#38238)

Co-authored-by: sglang-bot <sglang-bot@users.noreply.github.com>
2026-09-06 17:49:41 -07:00
parent 15aa2fb843
commit 6252993afe
1016 changed files with 1051 additions and 1051 deletions
@@ -21,7 +21,7 @@ from sglang.test.ci.ci_register import register_cuda_ci

 _HAS_CUDA = torch.cuda.is_available()

-register_cuda_ci(est_time=20, stage="base-b", runner_config="1-gpu-small")
+register_cuda_ci(est_time=10, stage="base-b", runner_config="1-gpu-small")

 DTYPE = torch.bfloat16
 HEAD_NUM = 2
@@ -14,7 +14,7 @@ from sglang.srt.mem_cache.pool_host.mha import (
 from sglang.test.ci.ci_register import register_cpu_ci
 from sglang.test.test_utils import CustomTestCase

-register_cpu_ci(est_time=5, suite="base-a-test-cpu")
+register_cpu_ci(est_time=11, suite="base-a-test-cpu")


 def _make_host(layout: str) -> AsymmetricMHATokenToKVPoolHost:
@@ -27,7 +27,7 @@ from sglang.srt.mem_cache.unified_cache.unified_tree_core_interface import (
 )
 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=1, suite="base-a-test-cpu")
+register_cpu_ci(est_time=8, suite="base-a-test-cpu")


 class TestBufferModeSidecar(unittest.TestCase):
@@ -22,7 +22,7 @@ Usage:

 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=10, suite="base-a-test-cpu")
+register_cpu_ci(est_time=11, suite="base-a-test-cpu")

 import unittest
 from array import array
@@ -13,7 +13,7 @@ from sglang.srt.mem_cache.memory_pool import ReqToTokenPool
 from sglang.srt.runtime_context import get_context
 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=5, suite="base-a-test-cpu")
+register_cpu_ci(est_time=11, suite="base-a-test-cpu")


 class _FakeAllocator:
@@ -8,7 +8,7 @@ from sglang.srt.mem_cache.dsa_cache_layer_split import LayerSplitDSATokenToKVPoo
 from sglang.test.ci.ci_register import register_cpu_ci
 from sglang.test.test_utils import CustomTestCase

-register_cpu_ci(est_time=1, suite="base-a-test-cpu")
+register_cpu_ci(est_time=10, suite="base-a-test-cpu")


 class TestDSALayerShardUtils(CustomTestCase):
@@ -22,7 +22,7 @@ import torch.multiprocessing as mp
 from sglang.test.ci.ci_register import register_cuda_ci
 from sglang.test.test_utils import CustomTestCase

-register_cuda_ci(est_time=120, stage="base-c", runner_config="4-gpu-b200")
+register_cuda_ci(est_time=28, stage="base-c", runner_config="4-gpu-b200")

 LAYER_NUM = 4
 PAGE_SIZE = 64
@@ -7,7 +7,7 @@ from sglang.srt.mem_cache.deepseek_v4_memory_pool import (
 from sglang.test.ci.ci_register import register_cpu_ci
 from sglang.test.test_utils import CustomTestCase

-register_cpu_ci(est_time=1, suite="base-a-test-cpu")
+register_cpu_ci(est_time=10, suite="base-a-test-cpu")


 class TestCompressStateWritePad(CustomTestCase):
@@ -21,7 +21,7 @@ from sglang.srt.mem_cache.embedding_cache_controller import (
 )
 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=5, suite="base-a-test-cpu")
+register_cpu_ci(est_time=10, suite="base-a-test-cpu")


 def _make_pool(num_pages=16, dim=4, page_size=2, modality="vision"):
@@ -27,7 +27,7 @@ import torch

 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=5, suite="base-a-test-cpu")
+register_cpu_ci(est_time=10, suite="base-a-test-cpu")


 def _loc_info(virtual_loc, swa_phys=None, full_phys=None):
@@ -20,7 +20,7 @@ from sglang.srt.mem_cache.pool_host.mla import MLATokenToKVPoolHost
 from sglang.test.ci.ci_register import register_cpu_ci
 from sglang.test.test_utils import CustomTestCase

-register_cpu_ci(est_time=5, suite="base-a-test-cpu")
+register_cpu_ci(est_time=10, suite="base-a-test-cpu")

 DCP_SIZE = 8
 PHYSICAL_PAGE = 64
@@ -14,7 +14,7 @@ Run with:

 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=10, suite="base-a-test-cpu")
+register_cpu_ci(est_time=11, suite="base-a-test-cpu")

 import os
 import shutil
@@ -27,7 +27,7 @@ from sglang.srt.mem_cache.pool_host.mha import (
 from sglang.srt.mem_cache.pool_host.mla import MLATokenToKVPoolHost
 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=1, suite="base-a-test-cpu")
+register_cpu_ci(est_time=10, suite="base-a-test-cpu")


 class _FakeBuffer:
@@ -9,7 +9,7 @@ import torch
 from sglang.test.ci.ci_register import register_cuda_ci
 from sglang.test.test_utils import CustomTestCase

-register_cuda_ci(est_time=5, stage="base-b", runner_config="1-gpu-small")
+register_cuda_ci(est_time=9, stage="base-b", runner_config="1-gpu-small")


@unittest.skipUnless(torch.cuda.is_available(), "CUDA required")
@@ -2,7 +2,7 @@

 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=5, suite="base-a-test-cpu")
+register_cpu_ci(est_time=12, suite="base-a-test-cpu")

 import os
 import shutil
@@ -2,7 +2,7 @@

 from sglang.test.ci.ci_register import register_cuda_ci

-register_cuda_ci(est_time=30, stage="base-b", runner_config="1-gpu-small")
+register_cuda_ci(est_time=16, stage="base-b", runner_config="1-gpu-small")

 import os
 import shutil
@@ -32,7 +32,7 @@ from sglang.srt.mem_cache.pool_host.mla import MLATokenToKVPoolHost
 from sglang.test.ci.ci_register import register_cpu_ci
 from sglang.test.test_utils import CustomTestCase

-register_cpu_ci(est_time=3, suite="base-a-test-cpu")
+register_cpu_ci(est_time=10, suite="base-a-test-cpu")

 MEMORY_POOL_HOST_MODULE = "sglang.srt.mem_cache.memory_pool_host"
 DSA_POOL_HOST_MODULE = "sglang.srt.mem_cache.pool_host.dsa"
@@ -17,7 +17,7 @@ from sglang.srt.server_args import ServerArgs, set_global_server_args_for_schedu
 from sglang.test.ci.ci_register import register_amd_ci, register_cuda_ci
 from sglang.test.test_utils import CustomTestCase

-register_cuda_ci(est_time=15, stage="base-b", runner_config="1-gpu-small")
+register_cuda_ci(est_time=10, stage="base-b", runner_config="1-gpu-small")
 register_amd_ci(est_time=15, stage="stage-b", runner_config="1-gpu-small-amd")

 PAGE_SIZE = 2
@@ -8,7 +8,7 @@ from sglang.srt.mem_cache.hiradix_cache import HiRadixCache
 from sglang.srt.mem_cache.unified_radix_cache import UnifiedRadixCache
 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=1, suite="base-a-test-cpu")
+register_cpu_ci(est_time=11, suite="base-a-test-cpu")


 class _FakeWork:
@@ -14,7 +14,7 @@ from sglang.srt.runtime_context import get_context
 from sglang.test.ci.ci_register import register_cpu_ci
 from sglang.test.test_utils import CustomTestCase

-register_cpu_ci(est_time=1, suite="base-a-test-cpu")
+register_cpu_ci(est_time=10, suite="base-a-test-cpu")


 class TestDeepSeekV4HiSparseAllocator(CustomTestCase):
@@ -18,7 +18,7 @@ from sglang.srt.model_executor.model_runner import ModelRunner
 from sglang.test.ci.ci_register import register_cpu_ci
 from sglang.test.test_utils import CustomTestCase

-register_cpu_ci(est_time=2, suite="base-a-test-cpu")
+register_cpu_ci(est_time=12, suite="base-a-test-cpu")


 def _make_model_runner(**attrs):
@@ -15,7 +15,7 @@ from sglang.srt.mem_cache.memory_pool import HybridLinearKVPool
 from sglang.test.ci.ci_register import register_cpu_ci
 from sglang.test.test_utils import CustomTestCase

-register_cpu_ci(est_time=1, suite="base-a-test-cpu")
+register_cpu_ci(est_time=11, suite="base-a-test-cpu")


 class _Pool:
@@ -53,7 +53,7 @@ import torch
 import sglang.kernels.jit as _jit_pkg
 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=5, suite="base-a-test-cpu")
+register_cpu_ci(est_time=6, suite="base-a-test-cpu")

 _KERNEL_DIR = Path(_jit_pkg.__file__).parent / "csrc" / "inkling"

@@ -19,7 +19,7 @@ Triton kernel.

 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=8, suite="base-a-test-cpu")
+register_cpu_ci(est_time=10, suite="base-a-test-cpu")

 import unittest
 from types import SimpleNamespace
@@ -21,7 +21,7 @@ envelope formula byte for byte.

 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=6, suite="base-a-test-cpu")
+register_cpu_ci(est_time=9, suite="base-a-test-cpu")

 import unittest

@@ -19,7 +19,7 @@ from sglang.srt.mem_cache.unified_cache.component_type import ComponentType
 from sglang.test.ci.ci_register import register_cpu_ci
 from sglang.test.test_utils import CustomTestCase

-register_cpu_ci(est_time=2, suite="base-a-test-cpu")
+register_cpu_ci(est_time=11, suite="base-a-test-cpu")


 class TestDevicePoolEntry(CustomTestCase):
@@ -25,7 +25,7 @@ from sglang.srt.mem_cache.unified_cache.unified_tree_core import UnifiedTreeCore
 from sglang.srt.mem_cache.unified_radix_cache import UnifiedTreeNode
 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=2, suite="base-a-test-cpu")
+register_cpu_ci(est_time=10, suite="base-a-test-cpu")

 N = 4  # concurrent distinct-prefix requests

@@ -3,8 +3,8 @@
 from sglang.srt.arg_groups.mamba_hook import handle_mamba_backend
 from sglang.test.ci.ci_register import register_cpu_ci, register_cuda_ci

-register_cpu_ci(est_time=2, suite="base-a-test-cpu")
-register_cuda_ci(est_time=5, stage="base-b", runner_config="1-gpu-small")
+register_cpu_ci(est_time=11, suite="base-a-test-cpu")
+register_cuda_ci(est_time=10, stage="base-b", runner_config="1-gpu-small")

 import argparse
 import unittest
@@ -5,7 +5,7 @@ import torch
 from sglang.srt.mem_cache.memory_pool import MambaPool
 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=5, suite="base-a-test-cpu")
+register_cpu_ci(est_time=10, suite="base-a-test-cpu")

 NUM_LAYERS = 2
 NUM_SLOTS = 3
@@ -28,7 +28,7 @@ from sglang.srt.server_args import ServerArgs, set_global_server_args_for_schedu
 from sglang.srt.utils import get_device
 from sglang.test.ci.ci_register import register_amd_ci, register_cuda_ci

-register_cuda_ci(est_time=10, stage="base-b", runner_config="1-gpu-small")
+register_cuda_ci(est_time=11, stage="base-b", runner_config="1-gpu-small")
 register_amd_ci(est_time=9, suite="stage-b-test-1-gpu-small-amd")


@@ -28,7 +28,7 @@ from sglang.srt.mem_cache.utils import (
 )
 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=8, suite="base-a-test-cpu")
+register_cpu_ci(est_time=15, suite="base-a-test-cpu")


 def _legacy_get_hash_str(token_ids, prior_hash=None):
@@ -19,7 +19,7 @@ from sglang.srt.runtime_context import get_context
 from sglang.test.ci.ci_register import register_cpu_ci
 from sglang.test.test_utils import CustomTestCase

-register_cpu_ci(est_time=2, suite="base-a-test-cpu")
+register_cpu_ci(est_time=11, suite="base-a-test-cpu")


 class TestHostKVCache(CustomTestCase):
@@ -5,7 +5,7 @@ import torch
 from sglang.srt.mem_cache.memory_pool import MiniMaxSparseKVPool
 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=5, suite="base-a-test-cpu")
+register_cpu_ci(est_time=10, suite="base-a-test-cpu")


 def _make_k_only_pool(start_layer: int = 0) -> MiniMaxSparseKVPool:
@@ -12,7 +12,7 @@ from sglang.srt.mem_cache.hicache_storage import (
 from sglang.test.ci.ci_register import register_cpu_ci
 from sglang.test.test_utils import CustomTestCase

-register_cpu_ci(est_time=1, suite="base-a-test-cpu")
+register_cpu_ci(est_time=11, suite="base-a-test-cpu")


 class ReplicateConfigWithGroupIds:
@@ -5,7 +5,7 @@ from unittest.mock import patch
 from sglang.test.ci.ci_register import register_cpu_ci
 from sglang.test.test_utils import CustomTestCase

-register_cpu_ci(est_time=1, suite="base-a-test-cpu")
+register_cpu_ci(est_time=11, suite="base-a-test-cpu")


 def _fake_mooncake_modules(fake_store_cls):
@@ -12,7 +12,7 @@ from sglang.srt.mem_cache.storage.mooncake_store.mooncake_store import (
 )
 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=5, suite="base-a-test-cpu")
+register_cpu_ci(est_time=11, suite="base-a-test-cpu")


 def _fake_mooncake_modules(fake_store_cls):
@@ -20,7 +20,7 @@ suite runs on CPU apart from the cases that skip themselves without CUDA.

 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=8, suite="base-a-test-cpu")
+register_cpu_ci(est_time=11, suite="base-a-test-cpu")

 import contextlib
 import random
@@ -5,7 +5,7 @@ import torch
 from sglang.srt.mem_cache.memory_pool import MHATokenToKVPoolMXFP8
 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=5, suite="base-a-test-cpu")
+register_cpu_ci(est_time=10, suite="base-a-test-cpu")

 LAYERS = 2
 PAGE_SIZE = 128
@@ -12,7 +12,7 @@ Runs on CPU — pure-torch advanced indexing, no Triton.

 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=6, suite="base-a-test-cpu")
+register_cpu_ci(est_time=8, suite="base-a-test-cpu")

 import unittest

@@ -9,7 +9,7 @@ from sglang.srt.mem_cache.allocator.paged import PagedTokenToKVPoolAllocator
 from sglang.test.ci.ci_register import register_cpu_ci
 from sglang.test.test_utils import CustomTestCase

-register_cpu_ci(est_time=2, suite="base-a-test-cpu")
+register_cpu_ci(est_time=8, suite="base-a-test-cpu")

 PAGE_SIZE = 2
 NUM_PAGES = 16
@@ -17,7 +17,7 @@ from sglang.srt.mem_cache.allocator.paged import PagedTokenToKVPoolAllocator
 from sglang.srt.mem_cache.common import _release_overallocated_kv_indices
 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=15, suite="base-a-test-cpu")
+register_cpu_ci(est_time=10, suite="base-a-test-cpu")

 PAGE_SIZE = 4
 NUM_PAGES = 64
@@ -26,7 +26,7 @@ from sglang.srt.mem_cache.layout.page_major import (
 from sglang.test.ci.ci_register import register_cpu_ci
 from sglang.test.test_utils import CustomTestCase

-register_cpu_ci(est_time=60, suite="base-a-test-cpu")
+register_cpu_ci(est_time=11, suite="base-a-test-cpu")


 class TestMLAEnvelopeTransferAddressing(CustomTestCase):
@@ -9,7 +9,7 @@ from sglang.srt.mem_cache.chunk_cache import PureSWAChunkCache
 from sglang.test.ci.ci_register import register_cpu_ci
 from sglang.test.test_utils import CustomTestCase

-register_cpu_ci(est_time=3, suite="base-a-test-cpu")
+register_cpu_ci(est_time=10, suite="base-a-test-cpu")


 class _FakeAllocator:
@@ -8,7 +8,7 @@ import torch

 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=5, suite="base-a-test-cpu")
+register_cpu_ci(est_time=10, suite="base-a-test-cpu")


 class _FakeQuantMethod:
@@ -9,7 +9,7 @@ from unittest.mock import patch
 from sglang.test.ci.ci_register import register_cpu_ci
 from sglang.test.test_utils import CustomTestCase

-register_cpu_ci(est_time=2, suite="base-a-test-cpu")
+register_cpu_ci(est_time=11, suite="base-a-test-cpu")


 class TestRadixCacheCppCacheSalt(CustomTestCase):
@@ -14,7 +14,7 @@ from sglang.srt.mem_cache.memory_pool import MHATokenToKVPool, ReqToTokenPool
 from sglang.srt.mem_cache.radix_cache import RadixCache, RadixKey
 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=8, suite="base-a-test-cpu")
+register_cpu_ci(est_time=10, suite="base-a-test-cpu")


 class TestSLRUAccuracy(unittest.TestCase):
@@ -20,7 +20,7 @@ Usage:
 from sglang.test.ci.ci_register import register_amd_ci, register_cuda_ci

 # CPU-based unit test, runs quickly on any GPU runner
-register_cuda_ci(est_time=15, stage="base-b", runner_config="1-gpu-small")
+register_cuda_ci(est_time=14, stage="base-b", runner_config="1-gpu-small")
 register_amd_ci(est_time=5, suite="stage-b-test-1-gpu-small-amd")

 import random
@@ -7,7 +7,7 @@ RadixCache.

 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=5, suite="base-a-test-cpu")
+register_cpu_ci(est_time=10, suite="base-a-test-cpu")

 import unittest
 import unittest.mock
@@ -2,7 +2,7 @@

 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=5, suite="base-a-test-cpu")
+register_cpu_ci(est_time=11, suite="base-a-test-cpu")

 import unittest
 from unittest.mock import MagicMock, patch
@@ -23,7 +23,7 @@ from sglang.srt.mem_cache.kv_cache_configurator import _pp_local_per_request_byt
 from sglang.test.ci.ci_register import register_cpu_ci
 from sglang.test.test_utils import CustomTestCase

-register_cpu_ci(est_time=5, suite="base-a-test-cpu")
+register_cpu_ci(est_time=11, suite="base-a-test-cpu")

 # temporal = (hv=4, v_dim=8, k_dim=8), num_k_heads_per_tp = 4, record_len = 8,
 # 2 layers. conv bf16 (2B), fp32 gate/beta (4B). Ring tensors (per slot, per
@@ -6,7 +6,7 @@ from sglang.srt.managers.schedule_batch import Req, ReqKvInfo
 from sglang.srt.mem_cache.memory_pool import HybridReqToTokenPool
 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=5, suite="base-a-test-cpu")
+register_cpu_ci(est_time=11, suite="base-a-test-cpu")

 MAMBA_STATE = object()

@@ -12,7 +12,7 @@ from unified_tree_core_inspection_interface import UnifiedTreeCoreInspectionInte

 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=90, suite="base-a-test-cpu")
+register_cpu_ci(est_time=17, suite="base-a-test-cpu")

 if shutil.which("cargo") is None:
    pytest.skip("the rust backend builds with cargo", allow_module_level=True)
@@ -11,7 +11,7 @@ import torch

 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=90, suite="base-a-test-cpu")
+register_cpu_ci(est_time=17, suite="base-a-test-cpu")

 if shutil.which("cargo") is None:
    pytest.skip("the rust backend builds with cargo", allow_module_level=True)
@@ -6,7 +6,7 @@ import test_unified_radix_cache_unittest as shared_suite

 from sglang.test.ci.ci_register import register_cuda_ci

-register_cuda_ci(est_time=180, stage="base-b", runner_config="1-gpu-small")
+register_cuda_ci(est_time=57, stage="base-b", runner_config="1-gpu-small")


 class RustBackendSuite(unittest.TestSuite):
@@ -10,7 +10,7 @@

 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=15, suite="base-a-test-cpu")
+register_cpu_ci(est_time=10, suite="base-a-test-cpu")

 import unittest
 from array import array
@@ -2,7 +2,7 @@

 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=5, suite="base-a-test-cpu")
+register_cpu_ci(est_time=10, suite="base-a-test-cpu")

 import ast
 import unittest
@@ -15,7 +15,7 @@ from sglang.srt.mem_cache.allocator.swa import SWATokenToKVPoolAllocator
 from sglang.test.ci.ci_register import register_cpu_ci
 from sglang.test.test_utils import CustomTestCase

-register_cpu_ci(est_time=2, suite="base-a-test-cpu")
+register_cpu_ci(est_time=11, suite="base-a-test-cpu")


 def _make_self(*, page_size: int, full_available: int, swa_available: int):
@@ -6,7 +6,7 @@ import torch
 from sglang.srt.mem_cache.swa_memory_pool import SWAKVPool
 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=5, suite="base-a-test-cpu")
+register_cpu_ci(est_time=10, suite="base-a-test-cpu")

 ROWS = 4

@@ -28,7 +28,7 @@ from sglang.srt.mem_cache.swa_radix_cache import SWARadixCache
 from sglang.srt.utils import get_device
 from sglang.test.ci.ci_register import register_amd_ci, register_cuda_ci

-register_cuda_ci(est_time=12, stage="base-b", runner_config="1-gpu-large")
+register_cuda_ci(est_time=13, stage="base-b", runner_config="1-gpu-large")
 register_amd_ci(est_time=10, suite="stage-b-test-1-gpu-small-amd")

 # ---------------------------------------------------------------------------
@@ -32,7 +32,7 @@ from sglang.srt.utils import get_device
 from sglang.test.ci.ci_register import register_amd_ci, register_cuda_ci
 from sglang.test.test_utils import CustomTestCase

-register_cuda_ci(est_time=12, stage="base-b", runner_config="1-gpu-small")
+register_cuda_ci(est_time=10, stage="base-b", runner_config="1-gpu-small")
 register_amd_ci(est_time=12, suite="stage-b-test-1-gpu-small-amd")


@@ -41,7 +41,7 @@ from sglang.srt.mem_cache.unified_cache.components.swa_component import SWACompo
 from sglang.srt.mem_cache.unified_memory_pool import MHASubPoolSpec, UnifiedKVPool
 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=20, suite="base-a-test-cpu")
+register_cpu_ci(est_time=11, suite="base-a-test-cpu")

 _DEV = "cpu"
 _SWA = ComponentType.SWA
@@ -27,7 +27,7 @@ import torch
 from sglang.srt.mem_cache.swa_memory_pool import SWAKVPool
 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=15, suite="base-a-test-cpu")
+register_cpu_ci(est_time=10, suite="base-a-test-cpu")

 _DEV = "cpu"
 _FULL_V_HEAD_DIM = 8
@@ -24,7 +24,7 @@ from sglang.srt.mem_cache.unified_radix_cache import UnifiedRadixCache
 from sglang.test.ci.ci_register import register_cpu_ci
 from sglang.test.test_utils import CustomTestCase

-register_cpu_ci(est_time=5, suite="base-a-test-cpu")
+register_cpu_ci(est_time=10, suite="base-a-test-cpu")


 def _cache_init_params(**kwargs) -> CacheInitParams:
@@ -12,7 +12,7 @@ import torch

 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=5, suite="base-a-test-cpu")
+register_cpu_ci(est_time=10, suite="base-a-test-cpu")

 # These tests stub out mori with a fake in-process module, so they need neither
 # a real mori install nor a GPU and run on NVIDIA / CPU CI.
@@ -34,7 +34,7 @@ from test_multi_ended_allocator import (
 from sglang.srt.mem_cache.allocator import unified_sub_pool as mea
 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=15, suite="base-a-test-cpu")
+register_cpu_ci(est_time=10, suite="base-a-test-cpu")


 def _swa_composite():
@@ -40,7 +40,7 @@ from sglang.srt.mem_cache.unified_memory_pool import (
 )
 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=15, suite="base-a-test-cpu")
+register_cpu_ci(est_time=10, suite="base-a-test-cpu")

 _DEV = "cpu"

@@ -22,7 +22,7 @@ from sglang.srt.mem_cache.unified_cache.unified_cache_linker import (
 from sglang.srt.mem_cache.unified_radix_cache import UnifiedRadixCache
 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=1, suite="base-a-test-cpu")
+register_cpu_ci(est_time=10, suite="base-a-test-cpu")


 class _FakeLinker(UnifiedCacheLinker):
@@ -29,7 +29,7 @@ import unittest

 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=20, suite="base-a-test-cpu")
+register_cpu_ci(est_time=10, suite="base-a-test-cpu")


 def _build(lazy: bool):
@@ -38,7 +38,7 @@ from sglang.srt.mem_cache.allocator import unified_sub_pool as mea
 from sglang.srt.mem_cache.allocator.base import BaseTokenToKVPoolAllocator
 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=20, suite="base-a-test-cpu")
+register_cpu_ci(est_time=10, suite="base-a-test-cpu")

 PAGE_SIZE = _PagedFixture.PAGE_SIZE

@@ -1,6 +1,6 @@
 from sglang.test.ci.ci_register import register_cuda_ci

-register_cuda_ci(est_time=4, stage="base-b", runner_config="1-gpu-small")
+register_cuda_ci(est_time=9, stage="base-b", runner_config="1-gpu-small")

 import unittest

@@ -31,7 +31,7 @@ import torch

 from sglang.test.ci.ci_register import register_amd_ci, register_cpu_ci

-register_cpu_ci(est_time=30, suite="base-a-test-cpu")
+register_cpu_ci(est_time=13, suite="base-a-test-cpu")
 register_amd_ci(est_time=30, stage="stage-b", runner_config="1-gpu-small-amd")


@@ -23,7 +23,7 @@ Addressing law under test:

 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=8, suite="base-a-test-cpu")
+register_cpu_ci(est_time=11, suite="base-a-test-cpu")

 import unittest
 from types import SimpleNamespace
@@ -53,7 +53,7 @@ import torch

 from sglang.test.ci.ci_register import register_cuda_ci

-register_cuda_ci(est_time=30, stage="base-b", runner_config="1-gpu-small")
+register_cuda_ci(est_time=8, stage="base-b", runner_config="1-gpu-small")

 _HAS_CUDA = torch.cuda.is_available()
 _DEV = "cuda"
@@ -28,7 +28,7 @@ import torch

 from sglang.test.ci.ci_register import register_cuda_ci

-register_cuda_ci(est_time=60, stage="base-b", runner_config="1-gpu-small")
+register_cuda_ci(est_time=10, stage="base-b", runner_config="1-gpu-small")

 _HAS_CUDA = torch.cuda.is_available()
 _DEV = "cuda"
@@ -23,7 +23,7 @@ GPU parity of the read/write kernels (set_mla_kv_buffer TMA path etc.) lives in

 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=8, suite="base-a-test-cpu")
+register_cpu_ci(est_time=10, suite="base-a-test-cpu")

 import unittest

@@ -36,7 +36,7 @@ from sglang.test.ci.ci_register import register_cpu_ci

 # Hermetic convention of this directory's pool tests: plain unittest.TestCase,
 # only ci_register imported (no heavy sglang.test.test_utils chain).
-register_cpu_ci(est_time=30, suite="base-a-test-cpu")
+register_cpu_ci(est_time=14, suite="base-a-test-cpu")

 _DEV = "cpu"

@@ -10,7 +10,7 @@ from sglang.srt.mem_cache.unified_radix_cache import UnifiedRadixCache
 from sglang.test.ci.ci_register import register_cpu_ci
 from sglang.test.test_utils import CustomTestCase

-register_cpu_ci(est_time=2, suite="base-a-test-cpu")
+register_cpu_ci(est_time=10, suite="base-a-test-cpu")


 class TestUnifiedRadixAllocationEviction(CustomTestCase):
@@ -42,7 +42,7 @@ from sglang.srt.utils import get_device
 from sglang.test.ci.ci_register import register_amd_ci, register_cuda_ci
 from sglang.test.test_utils import CustomTestCase

-register_cuda_ci(est_time=25, stage="base-b", runner_config="1-gpu-small")
+register_cuda_ci(est_time=29, stage="base-b", runner_config="1-gpu-small")
 register_amd_ci(est_time=25, suite="stage-b-test-1-gpu-small-amd")

 # ---------------------------------------------------------------------------
@@ -102,7 +102,7 @@ from sglang.srt.utils import get_device
 from sglang.test.ci.ci_register import register_amd_ci, register_cuda_ci
 from sglang.test.test_utils import CustomTestCase

-register_cuda_ci(est_time=50, stage="base-b", runner_config="1-gpu-small")
+register_cuda_ci(est_time=60, stage="base-b", runner_config="1-gpu-small")
 register_amd_ci(est_time=50, suite="stage-b-test-1-gpu-small-amd")

 # A dedicated test entry point overrides this without changing the process-wide
@@ -20,7 +20,7 @@ from sglang.srt.mem_cache.hybrid_cache.hybrid_pool_assembler import (
 from sglang.srt.mem_cache.unified_cache.components import ComponentType
 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=2, suite="base-a-test-cpu")
+register_cpu_ci(est_time=10, suite="base-a-test-cpu")


 def _mock_kvcache(cls):
@@ -10,7 +10,7 @@ import torch
 from sglang.srt.mem_cache.unified_radix_cache import UnifiedRadixCache
 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=2, suite="base-a-test-cpu")
+register_cpu_ci(est_time=7, suite="base-a-test-cpu")


 class TestUnifiedRadixLockRefScenarios(unittest.TestCase):
@@ -36,7 +36,7 @@ from sglang.srt.mem_cache.allocator.unified_hybrid_swa import (
 from sglang.srt.mem_cache.unified_memory_pool import MHASubPoolSpec, UnifiedKVPool
 from sglang.test.ci.ci_register import register_cpu_ci

-register_cpu_ci(est_time=10, suite="base-a-test-cpu")
+register_cpu_ci(est_time=8, suite="base-a-test-cpu")


 def _build(n_full: int, n_swa: int, full_layers: int, swa_layers: int):
@@ -41,7 +41,7 @@ from sglang.test.ci.ci_register import register_cpu_ci

 # Hermetic convention of this directory's pool tests: plain unittest.TestCase,
 # only ci_register imported (no heavy sglang.test.test_utils chain).
-register_cpu_ci(est_time=30, suite="base-a-test-cpu")
+register_cpu_ci(est_time=8, suite="base-a-test-cpu")

 _DEV = "cpu"

@@ -11,7 +11,7 @@ from sglang.srt.runtime_context import get_context, get_parallel
 from sglang.test.ci.ci_register import register_cpu_ci
 from sglang.test.test_utils import CustomTestCase

-register_cpu_ci(est_time=1, suite="base-a-test-cpu")
+register_cpu_ci(est_time=7, suite="base-a-test-cpu")


 class TestUnoAllocationSizing(CustomTestCase):